27

26

25

24

23

22

21

20

19

1

2

3

4

5

6

7

8

9

36

35

34

33

32

31

30

29

28

10

11

12

13

14

15

16

17

18

AV

DD

AGND1

DGND

GPIOV

DD

SPIV

DD

CS

SCLK

SDI

SDO

DAV

GPIOB3

GPIOB2

GPIOB1

GPIOB0

GPIOA3

GPIOA2

GPIOA1

GPIOA0

AMC7891

SBAS518A

– AUGUST 2011 – REVISED DECEMBER 2011

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

RHH PACKAGE

QFN-36

(TOP VIEW)

AMC7891 Pin Functions

PIN

I/O

DESCRIPTION

NO.

NAME

1

AVDD

I

Analog supply voltage. (4.75 V to 5.5 V)

2

AGND1

I

Analog ground. Ground reference point for all analog circuitry on the device, AGND. Connect AGND1 and

AGND2 to the same potential, AGND.

3

DGND

I

Digital ground. Ground reference point for all digital circuitry on the device. Ideally, AGND and DGND should

be at the same potential and must not differ by more than 0.3 V.

4

GPIOVDD

I

GPIO supply voltage. (1.8 V to 5.5 V)

Sets the GPIO operating voltage and threshold levels.

5

SPIVDD

I

Serial interface supply voltage. (1.8 V to 5.5 V)

Sets the serial interface operating voltage and threshold levels.

6

CS

I

Active low serial data enable. Schmitt-trigger logic input.

This input is the frame synchronization signal for the serial data. When this signal goes low, it enables the

input shift register and data is sampled on subsequent falling clock edges. The DAC output and register

settings update following the 24th clock. If CS goes high before the 23th clock edge, the command is

ignored.

7

SCLK

I

Serial interface clock. Schmitt-trigger logic input.

Maximum SCLK rate is 30MHz.

8

SDI

I

Serial interface data input. Schmitt-trigger logic input.

Data is clocked into the input shift register on each falling edge of SCLK.

9

SDO

O

Serial interface data output. The SDO pin is in high impedance when CS is high.

Data is clocked out of the input shift register on each rising edge of SCLK.

10

DACOUT3

O

DAC3 buffered output. (0 V to AVDD).

Can source/sink up to 10 mA.

2

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© 2011, Texas Instruments Incorporated

Product Folder Link(s): AMC7891