ADS7044

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SBAS682D – NOVEMBER 2014 – REVISED DECEMBER 2015

Electrical Characteristics (continued)

At TA = –40°C to 125°C, AVDD = 3 V, DVDD = 1.65 V to 3.6 V, fSAMPLE = 1 MSPS, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER-SUPPLY REQUIREMENTS

AVDD

Analog supply voltage

1.65

3

3.6

V

DVDD

Digital I/O supply voltage

1.65

3

3.6

V

At 1 MSPS with AVDD = 3 V

300

IAVDD

Analog supply current

At 100 kSPS with AVDD = 3 V

30

µA

At 1 MSPS with AVDD = 1.8 V

145

At 1 MSPS with AVDD = 3 V

900

PD

Power dissipation

At 100 kSPS with AVDD = 3 V

90

µW

At 1 MSPS with AVDD = 1.8 V

261

6.6 Timing Characteristics

All specifications are at TA = –40°C to 125°C, AVDD = 1.65 V to 3.6 V, DVDD = 1.65 V to 3.6 V, and CLOAD on SDO = 20 pF,

unless otherwise specified.

MIN

TYP

MAX

UNIT

TIMING SPECIFICATIONS

fTHROUGHPUT

Throughput

1

MSPS

tCYCLE

Cycle time

1

µs

tCONV

Conversion time

12.5 × tSCLK + tSU_CSCK

ns

tDV_CSDO

Delay time: CS falling to data enable

10

ns

Delay time: SCLK falling to (next) data valid on DOUT,

30

AVDD = 1.8 V to 3.6 V

tD_CKDO

ns

Delay time: SCLK falling to (next) data valid on DOUT,

50

AVDD = 1.65 V to 1.8 V

tDZ_CSDO

Delay time: CS rising to DOUT going to 3-state

5

ns

TIMING REQUIREMENTS

tACQ

Acquisition time

200

ns

fSCLK

SCLK frequency

0.016

16

MHz

tSCLK

SCLK period

62.5

ns

tPH_CK

SCLK high time

0.45

0.55

tSCLK

tPL_CK

SCLK low time

0.45

0.55

tSCLK

tPH_CS

CS high time

60

ns

tSU_CSCK

Setup time: CS falling to SCLK falling

15

ns

tD_CKCS

Delay time: last SCLK falling to CS rising

10

ns

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