MB85R1002A

4

DS501-00004-6v1E



FUNCTIONAL TRUTH TABLE

Note: L = VIL, H = VIH, X can be either H, L,

or

, Hi-Z = High Impedance

: Latch address and latch data at falling edge,

: Latch address and latch data at rising edge

*1 : OE control of the Pseudo-SRAM means the valid address at the falling edge of OE to read.

*2 : WE control of the Pseudo-SRAM means the valid address and data at the falling edge of WE to write.

Mode

CE1

CE2

WE

OE

LB

UB

I/O1 to I/O8

I/O9 to I/O16

Supply

Current

Standby Precharge

H

X

X

X

X

X

Hi-Z

Hi-Z

Standby

(ISB)

X

L

X

X

X

X

X

X

H

H

X

X

X

X

X

X

H

H

Read

H

H

L

L

L

Data Output

Data Output

Operation

(IDD)

L

H

Data Output

Hi-Z

H

L

Hi-Z

Data Output

L

H

L

L

L

Data Output

Data Output

L

H

Data Output

Hi-Z

H

L

Hi-Z

Data Output

Read

(Pseudo-SRAM,

OE control*1)

L

H

H

L

L

Data Output

Data Output

L

H

Data Output

Hi-Z

H

L

Hi-Z

Data Output

Write

H

L

H

L

L

Data Input

Data Input

L

H

Data Input

Hi-Z

H

L

Hi-Z

Data Input

L

L

H

L

L

Data Input

Data Input

L

H

Data Input

Hi-Z

H

L

Hi-Z

Data Input

Write

(Pseudo-SRAM,

WE control*2)

L

H

H

L

L

Data Input

Data Input

L

H

Data Input

Hi-Z

H

L

Hi-Z

Data Input