ADS830

11

SBAS086A

lower CMV as it increases the signal headroom of the

driving amplifier. The internal reference ladder has a nomi-

nal impedance of 800

Ω. Depending on the selected refer-

ence voltages, the required drive current will vary accord-

ingly and the external reference circuitry should be designed

to supply the maximum required current.

DIGITAL INPUTS AND OUTPUTS

Clock Input Requirements

Clock jitter is critical to the SNR performance of high speed,

high resolution Analog to Digital Converters. It leads to

aperture jitter (tA) which adds noise to the signal being

converted. The ADS830 samples the input signal on the

rising edge of the CLK input. Therefore, this edge should

have the lowest possible jitter. The jitter noise contribution

to total SNR is given by the following equation. If this value

is near your system requirements, input clock jitter must be

reduced.

Where: ƒIN is Input Signal Frequency

tA is rms Clock Jitter

Particularly in udersampling applications, special consider-

ation should be given to clock jitter. The clock input should

be treated as an analog input in order to achieve the highest

level of performance. Any overshoot or undershoot of the

clock signal may cause degradation of the performance.

When digitizing at high sampling rates, the clock should

have a 50% duty cycle (tH = tL), along with fast rise and fall

times of 2ns or less.

Digital Outputs

The output data format of the ADS830 is in positive Straight

Offset Binary code, see Table I. This format can easily

converted into the Two’s Binary Complement code by

inverting the MSB.

Digital Output Driver (VDRV)

The ADS830 features a dedicated supply pin for the output

logic drivers, VDRV, which is not internally connected to

the other supply pins. Setting the voltage at VDRV to +5V

or +3V, the ADS830 produces corresponding logic levels

and can directly interface to the selected logic family. The

output stages are designed to supply sufficient current to

drive a variety of logic families. However, it is recom-

mended to use the ADS830 with +3V logic supply. This will

lower the power dissipation in the output stages due to the

lower output swing and reduce current glitches on the supply

line which may affect the ac performance of the converter.

In some applications, it might be advantageous to decouple

the VDRV pin with additional capacitors or a pi-filter.

GROUNDING AND DECOUPLING

Proper grounding and bypassing, short lead length, and the

use of ground planes are particularly important for high

frequency designs. Multilayer PC boards are recommended

for best performance since they offer distinct advantages

like minimizing ground impedance, separation of signal

layers by ground layers, etc. The ADS830 should be treated

as an analog component. Whenever possible, the supply pins

should be powered by the analog supply. This will ensure

the most consistent results, since digital supply lines often

carry high levels of noise which otherwise would be coupled

into the converter and degrade the achievable performance.

All ground connections on the ADS830 are internally joined

together, obviating the design of split ground planes. The

ground pins (1, 18) should directly connect to an analog

ground plane which covers the PC board area around the

converter. While designing the layout, it is important to keep

the analog signal traces separated from any digital lines to

prevent noise coupling onto the analog signal path. Because

of its high sampling rate, the ADS830 generates high fre-

quency current transients and noise (clock feedthrough) that

are fed back into the supply and reference lines. This

requires that all supply and reference pins are sufficiently

bypassed. Figure 9 shows the recommended decoupling

scheme for the ADS830. In most cases 0.1

µF ceramic chip

capacitors at each pin are adequate to keep the impedance

low over a wide frequency range. Their effectiveness largely

depends on the proximity to the individual supply pin.

Therefore, they should be located as close to the supply pins

as possible. In addition, a larger bipolar capacitor (1

µF to

22

µF) should be placed on the PC board in proximity of the

converter circuit.

It is recommended to keep the capacitive loading on the data

lines as low as possible (

≤ 15pF). Higher capacitive loading

will cause larger dynamic currents as the digital outputs are

changing. Those high current surges can feed back to the

analog portion of the ADS830 and affect the performance. If

necessary, external buffers or latches close to the converter’s

output pins may be used to minimize the capacitive loading.

They also provide the added benefit of isolating the ADS830

from any digital noise activities on the bus coupling back

high frequency noise.

FIGURE 9. Recommended Bypassing for the Supply Pins.

1

GND

ADS830

+

0.1µF

+V

S

19

18

GND

10µF

+5V

VDRV

20

0.1µF

+3/+5V

Jitter SNR

t

rms signal to rms noise

IN A

=

ƒ

20

1

2

log π

+FS (IN = +3.5V)

1111 1111

+1/2 FS

1100 0000

+1LSB

1000 0001

Bipolar Zero (IN = 2.5V)

1000 0000

–1LSB

0111 1111

–1/2 FS

0100 0000

–FS (IN = +1.5V)

0000 0000

SINGLE-ENDED INPUT (2Vp-p)

STRAIGHT OFFSET BINARY

(IN = CMV)

(SOB)

TABLE I. Coding Table for the ADS830.