ADS5400IPZPR datasheet(22/58 Pages) TI2

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REFERENCE

INP

INN

CLKINP

CLKINN

SCLK

SDIO

SDO

CLKOUTAP

CLKOUTAN

OUTB[0-11]P

OUTB[0-11]N

ADS5400

CLOCK

DIVIDE

12-bit ADC

(3 stage pipeline)

VCM

VREF

OVER RANGE

DETECTOR,

SYNC and

DEMUX

OUTA [0-11]P

OUTA[0-11]N

OVRBP (SYNCOUTBP)

OVRBN (SYNCOUTBN)

RESETP (SYNCINP)

RESETN (SYNCINN)

SDENB

BUFFER

CLKOUTBP

CLKOUTBN

OVRAP (SYNCOUTAP )

OVRAN (SYNCOUTAN)

ENEXTREF

ENPWD

ENA1BUS

CONTROL

TEMP SENSOR

OFFSET ADJUST

PHASE ADJUST

GAIN ADJUST

BUS A

BUS B

ADS5400

SLAS611C – OCTOBER 2009 – REVISED JANUARY 2016

www.ti.com

7 Detailed Description

7.1 Overview

The ADS5400 is a 12-bit, 1-GSPS, monolithic pipeline ADC. Its bipolar transistor analog core operates from 5-V

and 3.3-V supplies, while the output uses a 3.3-V supply to provide LVDS-compatible digital outputs. The

conversion process is initiated by the falling edge of the external input clock. At the sampling instant, the

differential input signal is captured by the input track-and-hold (T&H), and the input sample is sequentially

converted by a series of lower resolution stages, with the outputs combined in a digital correction logic block.

Both the rising and the falling clock edges are used to propagate the sample through the pipeline every half clock

cycle. This process results in a data latency of 7 - 8.5 clock cycles (output mode dependent), after which the

output data is available as a 12-bit parallel word, coded in offset binary or two's complement format.

The user can select to accept the data at the full sample rate using one bus (bus A, latency 7 cycles), or

demultiplex the data into two buses (bus A and B, latency 7.5 or 8.5 cycles) at half rate. A serial peripheral

interface (SPI) is provided for adjusting operational modes, as well as for calibrations of analog gain, analog

offset and clock phase for inter-leaving multiple ADS5400. Die temperature readout using the SPI is provided.

SYNC and RESET modes exist for synchronizing output data across multiple ADS5400.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Input Configuration

The analog input for the ADS5400 consists of an analog pseudo-differential buffer followed by a bipolar transistor

track-and-hold (see Figure 25). The integrated analog buffer isolates the source driving the input of the ADC from

sampling glitches on the T&H and allows for the integration of a 100-

Ω differential input resistor. The input

common mode is set internally through a 500-

Ω resistor connected from half of the AVDD5 supply voltage to

each of the inputs. The parasitic package capacitance shown is with the package unsoldered. Once soldered,

depending on the board characteristics, one can expect another ~1pF at the analog input pins, which is board

dependent.

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