6.5 Electrical Characteristics (continued)

at TA = 25 °C, VS = VSOUT = ±15V, VICM = 0V, VREF = 0V, RL = 10kΩ connected to ground, and G = 1V/V (unless otherwise

noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Gain drift

TA = –40°C to +125°C

G = 2

±0.05

±1

ppm/°C

G ≠ 2

±0.2

±2

Gain nonlinearity

G = 0.5 to 20, VOUT = 10V

±2

±5

ppm

G = 50, 100, VOUT = 10V

TBD

TBD

TA = –40°C to +125°C,

VOUT = 10V

G ≤ 20

TBD

G = 50, 100

TBD

OUTPUT

VOUT

Output voltage(2)

No load, VSOUT = ±2.25V

VLVSS + 0.1

VLVDD – 0.1

V

RL = 10kΩ

VSOUT = ±2.25V

VLVSS + 0.2

VLVDD – 0.2

VSOUT = ±18V

VLVSS + 0.4

VLVDD – 0.4

CL

Load capacitance

Stable operation for capacitive load

100

pF

ISC

Short-circuit current

Continuous to VSOUT / 2

±45

mA

TA = –40°C to +125°C

±20

±60

FREQUENCY RESPONSE

BW

Bandwidth, –3dB

G < 10

6.2

MHz

G = 10, 20

4.2

G = 50, 100

2.4

SR

Slew rate

G = 0.5 to 100, VOUT > 5V

TBD

V/µs

Gain switching time

TBD

µs

REFERENCE INPUT

Reference input voltage

VLVSS

VLVDD

V

Reference input impedance

10

kΩ

Reference input current

VIN = 0V

140

µA

Reference gain to output

1

V/V

Reference gain error

VOUT = ±10V, within the linear operating range

0.01

0.05

%

INPUT STAGE POWER SUPPLY

IQ_input

Input stage quiescent current

VS+, VS–

VIN = 0V, VICM = 0V

3

3.7

mA

TA = –40°C to +125°C

4.6

OUTPUT STAGE POWER SUPPLY

IQ_output

Output stage quiescent current

LVDD, LVSS

VIN = 0V, VREF = 0V

1.3

1.8

mA

TA = –40°C to +125°C

2.2

DIGITAL LOGIC

VIL

Digital input logic low

A0, A1, A2 pins, referred to DGND

VDGND

VDGND + 0.8

V

VIH

Digital input logic high

A0, A1, A2 pins, referred to DGND

VDGND + 1.8

VS+

V

Digital input pin current

A0, A1, A2 pins

1.5

3

µA

VDGND

DGND voltage

VS–

(VS+) – 4

V

DGND reference current

4

10

µA

(1)

Differential Input voltage of the PGA848 amplifier (VIN = VIN+ – VIN-). The valid input range depends on input common-mode voltage

VICM, gain G, and reference voltage VREF. See Section 8.1.1

(2)

Output voltage VOUT = G × VIN + VREF if VIN, VICM, and VREF are in valid linear operating range. See Section 8.1.1

PGA848

SBOSAN4 – AUGUST 2025

www.ti.com

6

Submit Document Feedback

Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: PGA848