LM5045MHXSLASHNOPB.A datasheet(4/47 Pages) TI2

4 / 47 page

LM5045

SNVS699H – FEBRUARY 2011 – REVISED JANUARY 2015

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Pin Functions

I/O

DESCRIPTION

APPLICATION INFORMATION

NAME

HTSSOP

WQFN

AGND

Analog Ground

Connect directly to the Power Ground.

BST1

Bootstrap capacitors connected between BST1, 2 and SW1,

2 provide bias supply for the high side HO1, 2 gate drivers.

Gate Drive Bootstrap

External diodes are required between VCC and BST1, 2 to

BST2

charge the bootstrap capacitors when SW1, 2 are low.

An external opto-coupler connected to the COMP pin

sources current into an internal NPN current mirror. The

Input to the Pulse Width

PWM duty cycle is at maximum with zero input current, while

COMP

Modulator

1 mA reduces the duty cycle to zero. The current mirror

improves the frequency response by reducing the AC voltage

across the opto-coupler.

If CS exceeds 750 mV the PWM output pulse will be

terminated, entering cycle-by-cycle current limit. An internal

Current Sense Input

switch holds CS low for 40 nS after either output switches

high to blank leading edge transients.

HO1

High side PWM outputs capable of driving the upper

High Side Output Driver

MOSFET of the bridge with 1.5-A peak source and 2-A peak

HO2

sink current.

HS1

Common connection of the high side FET source, low side

Switch Node

FET drain and transformer primary winding.

HS2

LO1

Alternating output of the PWM gate driver. Capable of 1.5-A

Low Side Output Driver

peak source and 2-A peak sink current.

LO2

An external voltage divider from the input power supply sets

the shutdown level during an over-voltage condition.

Alternatively, an external NTC thermistor voltage divider can

OVP/OTP

Overvoltage Protection

be used to set the shutdown temperature. The threshold is

1.25 V. Hysteresis is set by an internal current that sources

20 µA of current into the external resistor divider.

PGND

Power Ground

Connect directly to Analog Ground

Modulation ramp for the PWM comparator. This ramp can be

a signal representative of the primary current (current mode)

RAMP

Input to PWM Comparator

or proportional to the input voltage (feed-forward voltage

mode). This pin is reset to GND at the end of every cycle.

The resistance connected between RD1 and AGND sets the

Synchronous Rectifier

RD1

delay from the falling edge of SR1 or SR2 and the rising

Leading Edge Delay

edge of HO2/LO1 or HO1/LO2, respectively.

The resistance connected between RD2 and AGND sets the

Synchronous Rectifier

RD2

delay from the falling edge of HO1/LO2 or HO2/LO1 and the

Trailing Edge Delay

rising edge of SR2 or SR1, respectively.

Maximum output current is 15 mA. Locally decouple with a

REF

Output of a 5V reference

0.1-µF capacitor.

Whenever the CS pin exceeds the 750-mV cycle-cycle

current limit threshold, 30-µA current is sourced into the RES

capacitor for the remainder of the PWM cycle. If the RES

capacitor voltage reaches 1.0 V, the SS capacitor is

discharged to disable the HO1, HO2, LO1, LO2 and SR1,

RES

Restart Timer

SR2 outputs. The SS pin is held low until the voltage on the

RES capacitor has been ramped between 2-V and 4-V eight

times by 10-µA charge and 5-µA discharge currents. After

the delay sequence, the SS capacitor is released to initiate a

normal start-up sequence.

The resistance connected between RT and AGND sets the

Oscillator Frequency

oscillator frequency. Synchronization is achieved by AC

RT/SYNC

Control and Frequency

coupling a pulse to the RT/SYNC pin that raises the voltage

Synchronization

at least 1.5 V above the 2-V nominal bias level.

A ramping current source from 0 to 100 µA is provided for

slope compensation in current mode control. This pin can be

Slope Compensation

SLOPE

connected through an appropriate resistor to the CS pin to

Current

provide slope compensation. If slope compensation is not

required, SLOPE must be tied to ground.

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