RT =

17100

FS

- 0.001(FS - 400)

LM5032

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SNVS344B – MARCH 2005 – REVISED DECEMBER 2014

Feature Description (continued)

7.3.3 Drivers Off, VCC Disable

Referring to Figure 14, Drivers Off and VCC Disable are internal signals which, when active disable portions of the

LM5032. If the UVLO pin is below 1.25V, or if the thermal shutdown activates, the VCC Disable line switches high

to disable the VCC regulator. UVLO also activates the Drivers Off signal to disable the output drivers, connect the

SS1, SS2, COMP1, COMP2 and RES pins to ground, and enable the 50 µA Soft-start current sources.

If the VCC voltage falls below the under-voltage threshold of 6.2V , the UVT comparator activates only the Drivers

Off signal. The output drivers are disabled but the VCC regulator is not disabled. Additionally, the CS1, CS2, SS1,

SS2, COMP1, COMP2 and RES pins are internally grounded, and the 50 µA Soft-start current sources are

enabled.

7.3.4 Oscillator

The oscillator frequency is set with an external resistor RT connected between the RT/SYNC and GND1 pins.

The resistor value is calculated from:

(1)

where FS is the desired oscillator frequency in kHz (maximum of 2 MHz), and RT is in kΩ. See Figure 7. The two

gate driver outputs (OUT1 and OUT2) switch at half the oscillator frequency and 180° out of phase with each

other. The voltage at the RT/SYNC pin is internally regulated at 2.0V. The RT resistor should be located as close

as possible to the LM5032 with short direct connections to the pins.

The LM5032 can be synchronized to an external clock by applying a narrow clock pulse to the RT/SYNC pin. See

the Applications Information section for details on this procedure. The RT resistor is always required, whether the

oscillator is free running or externally synchronized.

7.3.5 PWM Comparator/Slope Compensation

The PWM comparator of each controller compares a slope compensated current ramp signal with the loop error

voltage derived from the COMP pin. The COMP voltage is typically controlled by an external error

amplifier/optocoupler feedback circuit to regulate the converter output voltage. Internally, the voltage at the

COMP pin passes through two level shifting diodes and a gain reducing 3:1 resistor divider (see Figure 15). The

compensated current ramp signal is a combination of the current waveform at the CS pin, and an internally

generated ramp derived from the internal clock. At duty cycles greater than 50% current mode control circuits are

prone to subharmonic oscillation. By adding a small fixed ramp to the external current sense signal oscillations

can be avoided. The internal ramp has an amplitude of 45 µA and is sourced into an internal 2k

Ω resistor, and a

42 k

Ω resistor in parallel with the external impedance at the CS pin. The ramp current also flows through the

external impedance connected to the CS pin and thus, the amount of slope compensation can be adjusted by

varying the external circuit at the CS pin.

The output of the PWM comparator provides the pulse width information to the output drivers. This comparator is

optimized for speed in order to achieve minimum controllable duty cycles. The comparator’s output duty cycle is

0% for VCOMP ≤1.5V, and increases as VCOMP increases.

If either Soft-start pin is pulled low (internally or externally) the corresponding COMP pin is pulled down with it,

forcing the output duty cycle to zero. When the Soft-start pin voltage increases, the COMP pin is allowed to

increase. An internal 5 k

Ω resistor connected from COMP to an internal 5.0V supply provides a pull-up for the

COMP pin and bias current to the collector of the opto-coupler transistor.

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