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LSF0108 датащи(PDF) 68 Page - Nexperia B.V. All rights reserved |
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LSF0108 датащи(HTML) 68 Page - Nexperia B.V. All rights reserved |
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68 / 234 page  Low capacitance ESD protection for high-speed interfaces ESD protection Configuration Type Package Size (mm) 2 1 5 0.5 10 PESD5V0X2UMB DFN1006B-3 (SOT883B) 1.0 x 0.6 x 0.37 PESD5V0X2UM DFN1006-3 (SOT883) 1.0 x 0.6 x 0.48 0.8 15 PESD5V0X2UAMB DFN1006B-3 (SOT883B) 1.0 x 0.6 x 0.37 PESD5V0X2UAM DFN1006-3 (SOT883) 1.0 x 0.6 x 0.48 0.9 9 PESD5V0X1BT SOT23 2.9 x 1.3 x 1.0 0 80 0.6 30 NUP1301U SOT323 2.0 x 1.25 x 0.95 NUP1301 SOT23 2.9 x 1.3 x 1.0 NUP1301QA SOT1215 1.0 x 1.0 x 0.4 0 2 4 0.26 20 PUSB3BB2DF DFN0603-3 (SOT8013) 0.62 x 0.32 x 0.25 3 0 5.5 1 8 PRTR5V0U2X SOT143B 2.9 x 1.3 x 1.0 1.8 12 PRTR5V0U2AX 1 8 PRTR5V0U2F DFN1410-6 (SOT886) 1.45 x 1.0 x 0.48 4 0 3.3 0.75 25 PESD3V3X4UHM DFN1308-6 (SOT8006) 1.3 x 0.8 x 0.4 5.5 1 8 IP4220CZ6 SOT457 (SC-74) 2.9 x 1.5 x 1.0 PRTR5V0U4D 0.7 12 PUSB2X4D 2.9 x 1.5 x 1.0 PUSB2X4Y SOT363 (SC-88) 2.0 x 1.25 x 0.95 0.6 8 IP4283CZ10-TBR DFN2510A-10 (SOT1176) 2.5 x 1.0 x 0.48 0.5 10 IP4294CZ10-TBR PUSB3F96 PHDMI2F4 3.3 0.27 15 PUSB3FR4 5 PHDMI2FR4 0 4 3.3 0.17 PUSB3AB4 5 PHDMI2AB4 brb051 1 2 3 006aaa482 4 1 3 2 006aaa156 6 1 5 2 4 3 PIMC31_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 24 March 2009 2 of 13 NXP Semiconductors PIMC31 500 mA, 50 V NPN/PNP double RET; R1 = 1 kW, R2 = 10 kW 2. Pinning information 3. Ordering information 4. Marking 5. Limiting values Table 2. Pinning Pin Description Simplified outline Graphic symbol 1 GND (emitter) TR1 2 input (base) TR1 3 output (collector) TR2 4 GND (emitter) TR2 5 input (base) TR2 6 output (collector) TR1 13 2 4 5 6 65 4 1 23 R2 TR1 TR2 R1 R2 R1 006aaa143 Table 3. Ordering information Type number Package Name Description Version PIMC31 SC-74 plastic surface-mounted package (TSOP6); 6 leads SOT457 Table 4. Marking codes Type number Marking code PIMC31 ZH Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Per transistor; for the PNP transistor with negative polarity VCBO collector-base voltage open emitter - 50 V VCEO collector-emitter voltage open base - 50 V VEBO emitter-base voltage open collector - 5 V VI input voltage TR1 positive - +10 V negative - − 5V input voltage TR2 positive - +5 V negative - − 10 V 24 3, 8 001aai619 1 5 PUSB3F97 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 1 — 10 May 2017 2 of 14 Nexperia PUSB3F97 ESD protection for ultra high-speed interfaces 2. Pinning information 3. Ordering information 4. Marking 5. Limiting values [1] All pins to ground. Table 1. Pinning Pin Symbol Description Simplified outline Graphic symbol 1 CH1 channel 1 ESD protection 2 CH2 channel 2 ESD protection 3 GND ground 4 CH3 channel 3 ESD protection 5 CH4 channel 4 ESD protection 6 n.c. not connected 7 n.c. not connected 8 GND ground 9 n.c. not connected 10 n.c. not connected Table 2. Ordering information Type number Package Name Description Version PUSB3F97 DFN2510A-10 plastic extremely thin small outline package; no leads; 10 terminals; body 1 2.5 0.5 mm SOT1176-1 Table 3. Marking codes Type number Marking code PUSB3F97 96 Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VI input voltage 0.5 +5.5 V VESD electrostatic discharge voltage IEC 61000-4-2, level 4 [1] contact discharge 10 +10 kV air discharge 15 +15 kV Tamb ambient temperature 40 +85 C Tstg storage temperature 55 +125 C Nexperia NUP1301QA Ultra low capacitance ESD protection array NUP1301QA All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 13 November 2017 2 / 13 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1 A1 anode (diode 1) 2 K2 cathode (diode 2) 3 K1, A2 cathode (diode 1) and anode (diode 2) 4 K1, A2 cathode (diode1) and anode (diode2) Transparent top view 1 2 3 4 DFN1010D-3 (SOT1215) aaa-022858 A1 K2 K1, A2 6. Ordering information Table 3. Ordering information Package Type number Name Description Version NUP1301QA DFN1010D-3 DFN1010D-3: plastic thermal enhanced ultra thin small outline package; no leads; 3 terminals; body 1.1 x 1.0 x 0.37 mm SOT1215 7. Marking Table 4. Marking codes Type number Marking code NUP1301QA X 110 MARKING CODE (EXAMPLE) PIN 1 INDICATION MARK VENDOR CODE YEAR DATE CODE READING DIRECTION READING EXAMPLE: 11 01 10 aaa-008041 MARK-FREE AREA Fig. 1. DFN1010D-3 (SOT1215) binary marking code description © Nexperia B.V. 2017. All rights reserved IP4220CZ6 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 5 — 8 July 2011 2 of 9 Nexperia IP4220CZ6 Dual USB 2.0 integrated ESD protection 2. Pinning information 3. Ordering information 4. Marking 5. Limiting values 6. Recommended operating conditions Table 1. Pinning Pin Symbol Description Simplified outline Graphic symbol 1 I/O 1 ESD protection 2 GND ground 3 I/O 2 ESD protection 4 I/O 3 ESD protection 5VP supply voltage 6 I/O 4 ESD protection 13 2 4 56 018aaa142 1 2 3 6 5 4 Table 2. Ordering information Type number Package Name Description Version IP4220CZ6 SC-74 plastic surface-mounted package (TSOP6); 6 leads SOT457 Table 3. Marking codes Type number Marking code IP4220CZ6 20 Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VI input voltage 0 5.5 V VESD electrostatic discharge voltage IEC 61000-4-2, level 4, contact; all pins 8 +8 kV Tstg storage temperature 55 +125 C Table 5. Operating conditions Symbol Parameter Conditions Min Typ Max Unit Tamb ambient temperature 40 - +85 C Nexperia IP4285CZ6-TD ESD protection for high-speed interfaces 4. Pinning information Table 1. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1 LINE1 line 1 ESD protection for I/O signals 2 GND ground 3 LINE3 line 3 ESD protection for I/O signals 4 LINE4 line 4 ESD protection for I/O signals 5 n.c not connected 6 LINE6 line 6 ESD protection for I/O signals 1 3 2 4 5 6 TSOP6 (SOT457) 3 4 2 1 6 018aaa176 5. Ordering information Table 2. Ordering information Package Type number Name Description Version IP4285CZ6-TD TSOP6 plastic, surface-mounted package (SC-74) SOT457 6. Marking Table 3. Marking codes Type number Marking code IP4285CZ6-TD 85 IP4285CZ6-TD All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet 31 July 2018 2 / 10 Nexperia PUSB3FR4 ESD protection for ultra high-speed interfaces 4. Pinning information Table 1. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1 CH1 channel 1 ESD protection 2 CH2 channel 2 ESD protection 3 GND ground 4 CH3 channel 3 ESD protection 5 CH4 channel 4 ESD protection 6 n.c. not connected 7 n.c. no connection 8 GND ground 9 n.c. not connected 10 n.c. not connected Transparent top view 10 9 8 7 6 1 2 3 4 5 DFN2510A-10 (SOT1176-1) CH1 CH2 CH3 CH4 GND = aaa-016329 5. Ordering information Table 2. Ordering information Package Type number Name Description Version PUSB3FR4 DFN2510A-10 plastic, leadless extremely thin small outline package; 10 terminals; 0.5 mm pitch; 2.5 mm x 1 mm x 0.5 mm body SOT1176-1 6. Marking Table 3. Marking codes Type number Marking code PUSB3FR4 FR PUSB3FR4 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet 12 July 2018 2 / 15 Nexperia PHDMI2AB4 ESD protection for ultra high-speed interfaces 4. Pinning information Table 1. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1 LINE1 line 1 ESD protection 2 LINE2 line 2 ESD protection 3 GND ground 4 LINE3 line 3 ESD protection 5 LINE4 line 4 ESD protection 6 n.c. not connected 7 n.c. not connected 8 GND ground 9 n.c. not connected 10 n.c. not connected Transparent top view 10 9 8 7 6 1 2 3 4 5 DFN2510A-10 (SOT1176-1) aaa-019396 CH1 CH2 CH3 CH4 GND = 5. Ordering information Table 2. Ordering information Package Type number Name Description Version PHDMI2AB4 DFN2510A-10 plastic, leadless extremely thin small outline package; 10 terminals; 0.5 mm pitch; 2.5 mm x 1 mm x 0.5 mm body SOT1176-1 6. Marking Table 3. Marking codes Type number Marking code PHDMI2AB4 AB PHDMI2AB4 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet 8 June 2018 2 / 14 Products in bold red are under development Nexperia PUSB3AB2DF Extremely low clamping low capacitance ESD protection reverse dI dV Vhold Ihold It1 Vt1 V I forward aaa-027670 VRWM Rdyn = dV/dI Fig. 9. V-I characteristics for a bidirectional ESD protection diode 10. Application information The device is designed for the protection of two signal lines from surge pulses and ESD damage. The device is suitable on lines where the signal polarities are both, positive and negative with respect to ground. The device uses an advanced clamping structure showing a negative dynamic resistance. This snap-back behavior strongly reduces the clamping voltage system behind the ESD protection during an ESD event. Do not connect unlimited DC current sources to the data lines to avoid keeping the ESD protection device snap-back state after exceeding breakdown voltage (due to an ESD pulse for instance). aaa-030287 ESD protection diode GND lines to be protected Fig. 10. Application diagram Circuit board layout and protection device placement Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT) and surge transients. The following guidelines are recommended: 1. Place the device as close to the input terminal or connector as possible. 2. Minimize the path length between the device and the protected line. 3. Keep parallel signal paths to a minimum. 4. Avoid running protected conductors in parallel with unprotected conductors. 5. Minimize all Printed-Circuit Board (PCB) conductive loops including power and ground loops. 6. Minimize the length of the transient return path to ground. 7. Avoid using shared transient return paths to a common ground point. 8. Use ground planes whenever possible. For multilayer PCBs, use ground vias. PUSB3AB2DF All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved Product data sheet 22 November 2019 6 / 11 aaa-030288 Nexperia selection guide 2020 68 |
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