7.3.4 Output Stages

The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance,

and high peak current capability of both outputs allow for efficient switching of the power MOSFETs. The

low-side output stage is referenced to GND and the high-side is referenced to SH.

7.3.5 SH Transient Voltages Below Ground

In most applications, the body diode of the external low-side power MOSFET clamps the SH node to ground.

In some situations, board capacitance and inductance can cause the SH node to transiently swing several volts

below ground, before the body diode of the external low-side MOSFET clamps this swing. The SH pin in the

LM2103 is allowed to swing below ground as long as specifications are not violated and conditions mentioned in

this section are followed.

SH must always be at a lower potential than GH. Pulling GH more negative than specified conditions can

activate parasitic transistors which may result in excessive current flow from the BST supply. This may result

in damage to the device. The same relationship is true with GL and GND. If necessary, a Schottky diode can

be placed externally between GH and SH or GL and GND to protect the device from this type of transient. The

diode must be placed as close to the device pins as possible in order to be effective.

Low ESR bypass capacitors from BST to SH and from GVDD to GND are essential for proper operation of the

gate driver device. The capacitor should be located at the leads of the device to minimize series inductance.

The peak currents from GL and GH can be quite large. Any series inductance with the bypass capacitor causes

voltage ringing at the leads of the device which must be avoided for reliable operation.

7.4 Device Functional Modes

The device operates in normal mode and UVLO mode. See Section 7.3.1 for more information on UVLO

operation mode. In normal mode, when the VGVDD and VBST–SH are above UVLO threshold, the output stage is

dependent on the states of the INH and INL pins. The outputs GH and GL will be low if input state is floating.

Table 7-3. Input/Output Logic in Normal Mode of Operation

INH

INL

GH(1)

GL(2)

L

L

L

H

L

H

L

L

H

L

L

L

H

H

H

L

Floating

Floating

L

L

(1)

GH is measured with respect to SH.

(2)

GL is measured with respect to GND.

8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

To operate power MOSFETs at high switching frequencies and to reduce associated switching losses, a powerful

gate driver is employed between the PWM output of controller and the gates of the power semiconductor

devices. Also, gate drivers are indispensable when it is impossible for the PWM controller to directly drive the

gates of the switching devices. With the advent of digital power, this situation is often encountered because

the PWM signal from the digital controller is often a 3.3-V logic signal which cannot effectively turn on a power

switch. Level-shift circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) to

fully turn on the power device and minimize conduction losses. Traditional buffer drive circuits based on NPN

LM2103

SNVSC62A – APRIL 2023 – REVISED AUGUST 2023

www.ti.com

12

Submit Document Feedback

Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: LM2103