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PCF8545 датащи(PDF) 11 Page - NXP Semiconductors

номер детали PCF8545
подробное описание детали  Universal LCD driver for multiplex rates up to 1:8
PDF  72 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCF8545 датащи(HTML) 11 Page - NXP Semiconductors

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PCF8545
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 13 November 2013
11 of 72
NXP Semiconductors
PCF8545
Universal LCD driver for multiplex rates up to 1:8
• A clock signal must always be supplied to the device when the display is active.
Removing the clock may freeze the LCD in a DC state, which is not suitable for the
liquid crystal. First disable the display and afterwards remove the clock signal.
8.1.3.4
Display enable
The display enable bit (E) is used to enable and disable the display. When the display is
disabled, all LCD outputs go to VSS. This function is implemented to ensure that no
voltage can be induced on the LCD outputs as it may lead to unwanted displays of
segments.
Recommended start-up sequences are found in Section 8.2.3
Remark: Display enable is not synchronized to an LCD frame boundary. Therefore using
this function to flash a display for prolonged periods is not recommended due to the
possible build-up of DC voltages on the display.
8.1.4 Command: oscillator-control
The oscillator-control command switches between internal and external oscillator and
enables or disables the pin OSCCLK. It is also defines the external frequency.
[1]
Default value.
The bits OSC, COE, and EFR control the source and frequency of the clock used to
generate the LCD signals (see Figure 7). Valid combinations are shown in Table 11.
Table 10.
Oscillator-control - oscillator control command bit description
Bit
Symbol
Value
Description
7 to 3
-
00011
fixed value
2EFR
external clock frequency applied on pin
OSCCLK
0[1]
9.6 kHz
1
230 kHz
1COE
clock output enable for pin OSCCLK
0[1]
clock signal not available on pin OSCCLK;
pin OSCCLK is in 3-state
1
clock signal available on pin OSCCLK
0OSC
oscillator source
0[1]
internal oscillator running
1
external oscillator used;
pin OSCCLK becomes an input;
used in combination with EFR to determine
input frequency



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