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CDCM1802

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SCAS759C – APRIL 2004 – REVISED JULY 2017

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(1)

It is recommended to provide four thermal vias to connect the thermal pad of the package effectively with the PCB and ensure a good

heat sink.

11.3 Thermal Considerations

Table 2. Package Thermal Resistance

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RθJA

VQFN

−16 package thermal resistance

with thermal vias in PCB(1)

4-layer JEDEC test board (JESD51

−7) with four thermal

vias of 22-mil diameter each, airflow = 0 ft/min

48.4

°C/W

Example:

Calculation of the junction-lead temperature with a 4-layer JEDEC test board using four thermal vias:

TChassis = 85°C (temperature of the chassis)

Peffective = Imax × Vmax = 85 mA × 3.6 V = 306 mW (max power consumption inside the package)

ΔTJunction = RθJA × Peffective = 40.8°C/W × 306 mW = 12.48°C

TJunction = ΔTJunction + TChassis = 12.48°C + 85°C = 97.48°C (the maximum junction temperature of

Tdie−max = 125°C is not violated)