−150

−140

−130

−120

−110

−100

−90

−80

−70

−60

−50

foffset − Offset Frequency − Hz

G012

Phase Noise Comparison

fout = 135 MHz

27-MHz Crystal

Buffered Output

10

100

1k

10k

100k

1M

10M

fVCO = 270 MHz

fVCO = 135 MHz

PLL-Lock Time

CDCE706

www.ti.com ........................................................................................................................................... SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008

Phase noise is a result of random and discrete noise causing a broad slope and spurious peaks. The discrete

spurious components could be caused by known clock frequencies in the signal source, power line interference,

and mixer products. The broadening caused by random noise fluctuation is due to phase noise. It can be the

result of thermal noise, shot noise, and/or flicker noise in active and passive devices.

An important factor for the PLL synthesizer is the loop bandwidth (–3-dB cutoff frequency)—large loop bandwidth

(LBW) results in fast transient response but less reference spur attenuation. The LBW of the CDCE706 is about

100 kHz to 250 kHz, depending on the selected PLL parameter.

For the CDCE706, two phase-noise characteristics are of interest, the phase noise of the crystal-input stage and

the phase noise of the internal PLL (VCO). Figure 32 shows the respective phase noise characteristic.

Figure 32. Phase Noise Characteristic

Some applications use frequency switching, e.g., changing frequency in a TV application (switching between

channels) or changing the PCI-X frequency in computers. The time spent by the PLL in achieving the new

frequency is of main interest. The lock time is the time it takes to jump from one specified frequency to another

specified frequency within a given frequency tolerance (see Figure 33). It should be low, because a long lock

time impacts the data rate of the system.

The PLL-lock time depends on the device configuration and can be changed by the VCO frequency, i.e., by

changing the M/N divider values. Table 7 gives the typical lock times of the CDCE706 and Figure 33 shows a

snapshot of a frequency switch.

Table 7. CDCE706 PLL Lock-Times

Description

Lock Time

Unit

Frequency change via reprogramming of N/M counter

100

µs

Frequency change via CLK_SEL pin (switching between CLK_IN0 and CLK_IN1)

100

µs

Power-up lock time with system clock

50

µs

Power-up lock time with 27-MHz crystal at CLK_IN0 and CLK_IN1

300(1)

µs

(1)

Is the result of crystal lock time (200

µs) and PLL lock time (100 µs).

Copyright © 2005–2008, Texas Instruments Incorporated

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