ADS1625IPAPR datasheet(22/38 Pages) TI2

22 / 38 page

ADS1625

ADS1626

SBAS280E − JUNE 2003 − REVISED MAY 2007

www.ti.com

SETTLING TIME

The settling time is an important consideration when

measuring signals with large steps or when using a

multiplexer in front of the analog inputs. The ADS1625/6

digital filter requires time for an instantaneous change in

signal level to propagate to the output.

Be sure to allow the filter time to settle after applying a large

step in the input signal, switching the channel on a

multiplexer placed in front of the inputs, resetting the

ADS1625/6, or exiting the power-down mode.

Figure 17 shows the settling error as a function of time for a

full-scale signal step applied at t = 0. This figure uses DRDY

cycles for the time scale (X-axis). After 46 DRDY cycles, the

settling error drops below 0.001%. For fCLK = 40MHz, this

corresponds to a settling time of 36.8

µs.

101

100

10−1

10−2

10−3

10−4

Settling Time (DRDY cycles)

Figure 17. Settling Time

IMPULSE RESPONSE

Figure 18 plots the normalized response for an input applied

at t = 0. The X-axis units of time are DRDY cycles. As shown

in Figure 18, the peak of the impulse takes 26 DRDY cycles

to propagate to the output. For fCLK = 40MHz, a DRDY cycle

is 0.8

µs in duration and the propagation time (or group delay)

is 26

× 0.8µs = 20.8µs.

1.0

0.8

0.6

0.4

0.2

−0.2

−0.4

10203040

Time (DRDY cycles)

Figure 18. Impulse Response

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