TAS5622ADDVR datasheet(22/44 Pages) TI2

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TAS5622A

SLAS845A – MAY 2012 – REVISED MARCH 2015

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8.2.1.1 Design Requirements

See Figure 16 for application schematic. In this application, differential PWM inputs are used with AD modulation

from the PWM modulator (that is, TAS5558). AD modulation scheme is defined as PWM(+) is opposite polarity

from PWM(-).

8.2.1.2 Detailed Design Procedure

•

Pin 1 - GVDD_AB is the gate drive voltage for half-bridges A and B. It needs a 3.3-

Ω isolation resistor and a

0.1-µF decoupling capacitor.

•

Pin 2 - VDD is the supply for internal voltage regulators AVDD and DVDD. It needs a 10-µF bulk capacitor

and a 0.1-µF decoupling capacitor.

•

Pin 3 - Roc adjust is the overcurrent programming resistor. Depending on the application, this resistor can be

between 24 k

Ω to 68 kΩ.

•

Pin 4 - RESET pin when asserted, it keeps outputs high Z and no PWM switching. This pin can be controlled

by a microprocessor.

•

Pins 5 and 6 - These are PWM (+) and PWM (–) pins with signals provided by a PWM modulator such as

TAS5558. These are PWM differential pair.

•

Pin 7 - Start-up ramp capacitor should be 0.1 µF for BTL configuration.

•

Pin 8 - Digital output supply pin is connected to 1-µF decoupling capacitor.

•

Pins 9-12 - Ground pins are connected to board ground.

•

Pin 13 - Analog output supply pin is connected to 1-µF decoupling capacitor.

•

Pins 14 and 15 - These are PWM (+) and PWM (–) pins with signals provided by a PWM modulator such as

TAS5558. These are PWM differential pair.

•

Pin 16 - Fault pin can be monitored by a microcontroller through GPIO pin. System can decide to assert reset

or shutdown.

•

Pin 17 - Overtemperature warning pin can be monitored by a micro-controller through a GPIO pin. System

can decide to turn on fan or lower output power.

•

Pin 18 - Output clip indicator can be monitored by a microcontroller through a GPIO pin. System can decide

to lower the volume.

•

Pins 19-21 - Mode pins set the input and output configurations. For this configuration M1-M3 are grounded.

These mode pins must be hardware configured, such as, not through GPIO pins from a microcontroller.

•

Pin 22 - GVDD_CD is the gate drive voltage for half-bridges C and D. This pin needs a 3.3-

Ω isolation

resistor and a 0.1-µF decoupling capacitor.

•

Pins 23, 24, 43, 44 - Bootstrap pins for half-bridges A, B, C, and D. Connect 33 nF from this pin to

corresponding output pins.

•

Pins 25, 26, 33, 34, 41, 42 - These ground pins should be used to ground decoupling capacitors from

PVDD_X.

•

Pins 27, 28, 32, 35, 39, 40 - Output pins from half-bridges A, B, C, and D. Connect appropriate bootstrap

capacitors and differential LC filter as shown in Figure 16.

•

Pins 29, 30, 31, 36, 37, 38 - Power supply pins to half-bridges A, B, C, and D. A and B form a full-bridge and

C and D form another full-bridge. A 470-µF bulk capacitor is recommended for each full-bridge power pins.

Two 0.22-µF decoupling capacitors are placed on each full-bridge power pins. See Figure 16 for details.

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