TAS3103ADBT datasheet(13/154 Pages) TI2

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TERMINAL

PULLUP/

DOWN(2)

DESCRIPTION

NAME

PULLUP/

DOWN(2)

DESCRIPTION

TYPE(1)

I/O

NO.

I2C_SCL

I/O

I2C_SCL is the I2C clock pin. When the TAS3103A I2C port is a master,

I2C_SCL is (1/2N)

× (1/(M+1)) × 1/10 times the microprocessor clock, where N

and M are set to 2 and 8, respectively. When the TAS3103A I2C port is a slave,

input clock rates up to 400 kHz can be supported. This pin must be provided an

external pullup (2 k

Ω is recommended for most applications).

External

pullup

required

I2C_SDA

I/O

I2C_SDA is the I2C bidirectional data pin. The TAS3103A I2C port can support

data rates up to 400 kbps. This pin must be provided an external pullup (2 k

Ω is

recommended for most applications).

External

pullup

required

LRCLK

I/O

LRCLK is either an input or an output, depending on whether the TAS3103A is

in a master or slave serial audio port mode, which is determined by bit 22 of

subaddress 0xF9.

Pulldown

MCLKI

MCLKI is a master clock input that provides an alternative to using a fixed

crystal frequency. In DPLL modes, the input frequency of this clock can range

from 2.8 MHz to 24.576 MHz. In PLL bypass mode, frequencies up to 136 MHz

can be used. Whenever MCLKI is not used and XTALI/XTALO provide the

master clock input, MCLKI must be grounded.

None

MCLKO

MCLKO is the master output clock pin. It is produced by dividing MCLKI/XTALI

by 1, 2, or 4 (depending on the setting of a subaddress control field). MCLKO is

provided to interconnect, without the need for additional glue logic, the

TAS3103A interfaces with chips that require different multiples of the audio

sample rate (Fs) as a master clock.

None

MICROCLK_DIV

MICROCLK_DIV sets the division ratio between the digital audio processing

clock and the internal microprocessor clock. The audio-processing clock is the

DPLL output clock if PLL_bypass is not enabled. The audio-processing clock

is MCLKI/XTALI master clock if PLL_bypass is enabled. Logic high on this pin

sets the microprocessor clock equal to the audio-processing clock. A logic low

sets the microprocessor clock to 1/4 the digital audio-processing clock.

MICROCLK_DIV must be set low if the audio processing clock is > 36 MHz.

MICROCLK_DIV must be set high if the audio processing clock is

≤ 36 MHz.

Pulldown

ORIN

ORIN allows the processing of a multichannel signal set through two

TAS3103As without any additional components. One use of ORIN would be to

fully emulate a 6-channel audio processor at speeds up to a 96-kHz sample

rate with only two TAS3103As and no glue logic.

The two-chip configuration is accomplished by wiring the SDOUT1 port of one

of the two TAS3103A chips to the ORIN port of the second TAS3103A. Internal

to the chip, the ORIN input is ORed with internal SDOUT1 data to generate the

resulting output data on channel SDOUT1. For TDM output formats, the

SDOUT1 outputs of the two chips differ in phasing in both the left and right

channels to arrive at the proper composite output. For discrete outputs, one

chip contributes the left channel of the composite SDOUT1, and the other chip

contributes the right channel of the composite SDOUT1.

If not used, ORIN must be connected to ground.

Pulldown

PLL0

PLL0 is the LSB of a 2-bit code used to select four different modes of DPLL

multiplexer/input divider operation. PLL[1:0] values of 00, 01, and 10 select

the DPLL input clock to be MCLKI/XTALI divided by 1, 2, and 4, respectively. A

value of 11 results in MCLKI/XTALI being substituted for the DPLL output. The

pullup/pulldown combination provides a default of 01 when neither PLL0 nor

PLL1 is connected.

Pullup

PLL1

PLL1 is the MSB of a 2-bit code used to select four different modes of DPLL

multiplexer/input divider operation. PLL[1:0] values of 00, 01, and 10 select

the DPLL input clock to be MCLKI/XTALI divided by 1, 2, and 4, respectively. A

value of 11 results in MCLKI/XTALI being substituted for the DPLL output. The

pullup/pulldown combination provides a default of 01 when neither PLL0 nor

PLL1 is connected.

Pulldown

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