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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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RF430CL331H датащи(PDF) 36 Page - Texas Instruments |
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RF430CL331H датащи(HTML) 36 Page - Texas Instruments |
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36 / 63 page  RF430CL331H SLASE18A – SEPTEMBER 2015 – REVISED NOVEMBER 2015 www.ti.com Table 5-11. General Control Register Description (continued) BIT FIELD TYPE RESET DESCRIPTION Global interrupt output enable 0b = Interrupt output disabled. The INTO pin is Hi-Z. 2 Enable INT R/W 0 1b = Interrupt output enabled. The INTO pin signals any enabled interrupt according to the INTO High and INTO Drive bits. Global enable of RF interface. This bit must be set before the PICC can respond to any RF commands. 1 Enable RF R/W 0 0b = RF interface disabled 1b = RF interface enabled Software reset 0b = Always reads 0. 0 SW-Reset W 0 1b = Resets the device to default settings and clears memory. The serial communication is restored after tReady, and the register settings and NDEF memory must be restored afterward. 36 Detailed Description Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: RF430CL331H |
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