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LPV811, LPV812

SNOSD33B – NOVEMBER 2016 – REVISED NOVEMBER 2016

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8.3 Do's and Don'ts

Do properly bypass the power supplies.

Do add series resistance to the output when driving capacitive loads, particularly cables, Muxes and ADC inputs.

Do add series current limiting resistors and external schottky clamp diodes if input voltage is expected to exceed

the supplies. Limit the current to 1mA or less (1KΩ per volt).

9 Power Supply Recommendations

The LPV81x is specified for operation from 1.6 V to 5.5 V (±0.8 V to ±2.75 V) over a –40°C to 125°C temperature

range. Parameters that can exhibit significant variance with regard to operating voltage or temperature are

presented in the Typical Characteristics.

CAUTION

Supply voltages larger than 6 V can permanently damage the device.

For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines it is

suggested that 100 nF capacitors be placed as close as possible to the operational amplifier power supply pins.

For single supply, place a capacitor between V+ and V– supply leads. For dual supplies, place one capacitor

between V+ and ground, and one capacitor between V– and ground.

Low bandwidth nanopower devices do not have good high frequency (> 1 kHz) AC PSRR rejection against high-

frequency switching supplies and other 1 kHz and above noise sources, so extra supply filtering is recommended

if kilohertz or above noise is expected on the power supply lines.

10 Layout

10.1 Layout Guidelines

The V+ pin should be bypassed to ground with a low ESR capacitor.

The optimum placement is closest to the V+ and ground pins.

Care should be taken to minimize the loop area formed by the bypass capacitor connection between V+ and

ground.

The ground pin should be connected to the PCB ground plane at the pin of the device.

The feedback components should be placed as close to the device as possible to minimize strays.

10.2 Layout Example

Figure 50. SOT-23 Layout Example (Top View)