LP8551 datasheet(12/46 Pages) TI2

12 / 46 page

5 MHz internal

oscillator

PWM generation

PWM_FREQ[4:0]

or External

set resistor RFSET

VBOOST

LED Drivers 1-4

Divider

1/N

5 MHz...40 MHz

PSPWM 0/1

Boost

Filter

VCO

Counter

1/N

PLL

Phase

Detector

State machine,

PWM input, internal

timings, Slope etc.

BOOST_FREQ

N = 4, 8, 16, 32

PWM_RESOLUTION[1:0]

LP8551

SNVS673E – APRIL 2010 – REVISED SEPTEMBER 2014

www.ti.com

8.3 Feature Description

8.3.1 Clock Generation

The LP8551 has internal 5-MHz oscillator which is used for clocking the boost converter, state machine, PWM

outputs, PWM input duty cycle measurement, internal timings such as slope time for output brightness changes.

For PWM output generation the 5-MHz clock can be multiplied with the internal PLL to achieve higher resolution.

The higher the clock frequency for PWM generation block, the higher the resolution but the tradeoff is higher IQ

of the part. Clock multiplication is set with <PWM_RESOLUTION[1:0]> EEPROM Bits.

Figure 8. Principle of the Clock Generation

8.3.2 Brightness Control Methods

The LP8551 controls the brightness of the backlight with PWM. PWM control is received either from PWM input

pin or from I2C register bits. The PWM source selection is done with <BRT_MODE[1:0]> bits as follows:

BRT_MODE[1]

BRT_MODE[0]

PWM SOURCE

PWM input pin duty cycle control. Default.

PWM input pin duty cycle control.

Brightness register

PWM direct control (PWM in = PWM out)

8.3.2.1 PWM Input Duty Cycle

With PWM input pin duty cycle control the output PWM is controlled by PWM input duty cycle. PWM detector

block measures the duty cycle in the PWM pin and uses this 13-bit value to generate the output PWM. Output

PWM can have different frequency than input in this mode and also phase shift PWM mode can be used. Slope

is effective in this mode. PWM input resolution is defined by the input PWM clock frequency.

8.3.2.2 Brightness Register Control

With brightness register control the output PWM is controlled with 8-bit resolution <BRT7:0> register bits. Phase

shift scheme can be used with this, and the output PWM frequency can be freely selected. Slope is effective in

this mode.

8.3.2.3 PWM Direct Control

With PWM direct control the output PWM directly follows the input PWM. Due to the internal logic structure the

input is anyway clocked with the 5 MHz clock or the PLL clock. PSPWM mode is not possible in this mode. Slope

is not effective in this mode.

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