7A

COUTJ

(0.165V - 7A x 0.003) x (

)

350e3

3.3V

J458 2F

Istep

COUTJ

(VOUT - ISTEP x ESR) x (

)

fSW

VOUT

1.07k

Rfbb

2.26k

Rfbt

107

Rtkb

226

Rtkt

SS

3.3V Master

FB

2.5Vout

50 2A

Int VCC

LMZ23608

www.ti.com

SNVS708G – MARCH 2011 – REVISED AUGUST 2015

8.2.2.5 Tracking Supply Divider Option

The tracking function allows the module to be connected as a slave supply to a primary voltage rail (often the

3.3-V system rail) where the slave module output voltage is lower than that of the master. Proper configuration

allows the slave rail to power up coincident with the master rail such that the voltage difference between the rails

during ramp-up is small (that is, < 0.15 V typical). The values for the tracking resistive divider must be selected

such that the effect of the internal 50-µA current source is minimized. In most cases the ratio of the tracking

divider resistors is the same as the ratio of the output voltage setting divider. Proper operation in tracking mode

dictates the soft-start time of the slave rail be shorter than the master rail; a condition that is easy to satisfy

because the CSS cap is replaced by RTKB. The tracking function is only supported for the power up interval of the

master supply; once the SS/TRK rises past 0.795 V the input is no longer enabled and the 50-µA internal current

source is switched off.

Figure 52. Tracking Option Input Detail

8.2.2.6 COUT Selection

None of the required COUT output capacitance is contained within the module. A minimum value ranging from 330

μF for 6-VOUT to 660 μF for 1.2-VOUT applications is required based on the values of internal compensation in the

error amplifier. These minimum values can be decreased if the effective capacitor ESR is higher than 15 m

Ω.

A Low ESR (15-m

Ω) tantalum, organic semiconductor or specialty polymer capacitor types in parallel with a 47-

nF X7R ceramic capacitor for high frequency noise reduction is recommended for obtaining lowest ripple. The

output capacitor COUT may consist of several capacitors in parallel placed in close proximity to the module. The

output voltage ripple of the module depends on the equivalent series resistance (ESR) of the capacitor bank, and

can be calculated by multiplying the ripple current of the module by the effective impedance of your chosen

output capacitors (for ripple current calculation, see Equation 14). Electrolytic capacitors will have large ESR and

lead to larger output ripple than ceramic or polymer types. For this reason a combination of ceramic and polymer

capacitors is recommended for low output ripple performance.

The output capacitor assembly must also meet the worst case ripple current rating of

ΔiL, as calculated in

Equation 14 below. Loop response verification is also valuable to confirm closed loop behavior.

For applications with dynamic load steps; the following equation provides a good first pass approximation of COUT

for load transient requirements.

(8)

For 12 VIN, 3.3 VOUT, a transient voltage of 5% of VOUT = 0.165 V (ΔVOUT), a 7-A load step (ISTEP), an output

capacitor effective ESR of 3 m

Ω, and a switching frequency of 350 kHz (fSW):

(9)

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