LMZ22010

SNVS687H – MARCH 2011 – REVISED AUGUST 2015

www.ti.com

Feature Description (continued)

Figure 46. Output Voltage Ripple of Two Modules With

Figure 47. Output Voltage Ripple of Two Modules With

Synchronization Clocks in Phase

Synchronization Clocks 180 Degrees Out of Phase

7.3.3 Output Overvoltage Protection

If the voltage at FB is greater than a 0.86V internal reference, the output of the error amplifier is pulled toward

ground, causing VOUT to fall.

7.3.4 Current Limit

The LMZ22010 is protected by both low-side (LS) and high-side (HS) current limit circuitry. The LS current limit

detection is carried out during the OFF-time by monitoring the current through the LS synchronous MOSFET.

Referring to the Functional Block Diagram, when the top MOSFET is turned off, the inductor current flows

through the load, the PGND pin and the internal synchronous MOSFET. If this current exceeds 13 A (typical) the

current limit comparator disables the start of the next switching period. Switching cycles are prohibited until

current drops below the limit.

NOTE

DC current limit is dependent on duty cycle as illustrated in the graph in the Typical

Characteristics section.

The HS current limit monitors the current of top side MOSFET. Once HS current limit is detected (16 A typical) ,

the HS MOSFET is shutoff immediately, until the next cycle. Exceeding HS current limit causes VOUT to fall.

Typical behavior of exceeding LS current limit is that fSW drops to 1/2 of the operating frequency.

7.3.5 Thermal Protection

The junction temperature of the LMZ22010 must not be allowed to exceed its maximum ratings. Thermal

protection is implemented by an internal Thermal Shutdown circuit which activates at 165°C (typical) causing the

device to enter a low power standby state. In this state the main MOSFET remains off causing VOUT to fall, and

additionally the CSS capacitor is discharged to ground. Thermal protection helps prevent catastrophic failures for

accidental device overheating. When the junction temperature falls back below 150°C (typical hysteresis = 15°C)

the SS pin is released, VOUT rises smoothly, and normal operation resumes.

Applications requiring maximum output current especially those at high input voltage may require additional

derating at elevated temperatures.

7.3.6 Prebiased Start-Up

The LMZ22010 will properly start up into a prebiased output. This startup situation is common in multiple rail

logic applications where current paths may exist between different power rails during the startup sequence. The

following scope capture shows proper behavior in this mode. Trace one is Enable going high. Trace two is 1.8-V

prebias rising to 3.3 V. Trace three is the SS voltage with a CSS= 0.47 µF. Rise-time determined by CSS.

16

Submit Documentation Feedback

Copyright © 2011–2015, Texas Instruments Incorporated

Product Folder Links: LMZ22010