DAC1282IPWR datasheet(21/48 Pages) TI2

21 / 48 page

2 k

Output

Amplifier

CAPP

VOUTP

VOUTN

CAPN

Current

DAC

1 nF

2 k

5 V

Reference

0.1 µF

(1)

VREF

AVSS (14)

-2.5 V

220 k

Power-down

Switch

Internal

Circuitry

AVSS (23)

DAC1282, DAC1282A

www.ti.com

SBAS490B – DECEMBER 2011 – REVISED MAY 2015

8.2.3 Reference Voltage (VREF)

The DAC1282 requires an external reference for operation. Although reference voltage as low as 2.5 V can be

used, best SNR is achieved with a 5-V reference. The reference input is defined as the voltage difference

between VREF and AVSS (that is, VREF = VREF – AVSS). The DAC1282 output scales with VREF; consequently,

reference noise or drift appears on the DAC output. Excessive reference noise may lead to degraded SNR. A

low-drift and low-noise reference is recommended.

Connect the external reference ground pin directly to the AVSS pins using a star connector to AVSS pin 14. Star

connection minimizes the possibility of power-supply crosstalk. Also, connect a 0.1-µF capacitor close to the

VREF and AVSS terminals to reduce noise susceptibility. Figure 35 shows the reference connection. The

reference input impedance is 220 k

Ω. In power-down the switch is off, resulting in very high input impedance. For

single-supply applications, connect AVSS to a clean analog ground point.

(1) Recommended bypass capacitor.

Figure 35. Reference Input Connection

8.2.4 Output Filter (CAPP, CAPN)

The CAPP and CAPN pins are the connections for two external capacitors, one capacitor connects to CAPP and

VOUTP and the other capacitor connects to CAPN and VOUTN. The capacitors are required to filter the DAC

sampling noise. The capacitor values are 1 nF; capacitors with low voltage coefficients should be used (C0G

ceramic or film).

As seen in Figure 36, the external capacitors form an analog low-pass filter with the internal feedback resistors.

After step changes to the data in the sine, dc, and digital data modes, the settling of the DAC and the analog

filter is 100-µs typical, as shown in Figure 46. In pulse mode, the filter is internally disabled, yielding shorter

settling time.

Figure 36. Output Filter

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