6 Detailed Description

6.1 Overview

The CDx4HC147 and CD74HCT147 devices are high speed silicon-gate CMOS devices and are pin-compatible

with low power Schottky TTL (LSTTL).

The CDx4HC147 and CD74HCT147 9-input priority encoders accept data from nine active LOW inputs (l1 to l9)

and provide binary representation on the four active LOW outputs (Y0 to Y3). A priority is assigned to each input

so that when two or more inputs are simultaneously active, the input with the highest priority is represented on

the output, with input line l9 having the highest priority.

These devices provide the 10-line to 4-line priority encoding function by use of the implied decimal “zero”. The

“zero” is encoded when all nine data inputs are HIGH, forcing all four outputs HIGH.

6.2 Functional Block Diagram

Figure 6-1. Functional Block Diagram

6.3 Device Functional Modes

Function Table lists the functional modes of the CDx4HC(T)147.

Table 6-1. Truth Table

(1) (2) (3)

INPUTS

OUTPUTS

I1

I2

I3

I4

I5

I6

I7

I8

I9

Y3

Y2

Y1

Y0

H

H

H

H

H

H

H

H

H

H

H

H

H

X

X

X

X

X

X

X

X

L

L

H

H

L

X

X

X

X

X

X

X

L

H

L

H

H

H

X

X

X

X

X

X

L

H

H

H

L

L

L

X

X

X

X

X

L

H

H

H

H

L

L

H

X

X

X

X

L

H

H

H

H

H

L

H

L

X

X

X

L

H

H

H

H

H

H

L

H

H

X

X

L

H

H

H

H

H

H

H

H

L

L

X

L

H

H

H

H

H

H

H

H

H

L

H

L

H

H

H

H

H

H

H

H

H

H

H

L

(1)

H = High logic level

(2)

L = Low logic level

(3)

X = Don't care

CD54HC147, CD74HC147, CD74HCT147

SCHS149G – NOVEMBER 1998 – REVISED JANUARY 2025

www.ti.com

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