TPS54873PWPR datasheet(13/24 Pages) TI2

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TPS54873

SLVS444A − OCTOBER 2002 − REVISED FEBRUARY 2005

www.ti.com

DISABLED SINKING DURING START-UP

(DSDS)

The DSDS feature enables minimal voltage drooping of

output precharge capacitors at start-up. The TPS54873

is designed to disable the low-side MOSFET to prevent

sinking current from a precharge output capacitor during

start-up. Once the high-side MOSFET has been turned on

to the maximum duty cycle limit, the low-side MOSFET is

allowed to switch. Once the maximum duty cycle condition

is met, the converter functions as a sourcing converter until

the SS/ENA is pulled low.

UNDERVOLTAGE LOCK OUT (UVLO)

The TPS54873 incorporates an under voltage lockout

circuit to keep the device disabled when the input voltage

(VIN) is insufficient. During power up, internal circuits are

held inactive until VIN exceeds the nominal UVLO

threshold voltage of 3.8 V. Once the UVLO start threshold

is reached, device start-up begins. The device operates

until VIN falls below the nominal UVLO stop threshold of

3.5 V. Hysteresis in the UVLO comparator and a 2.5-µs

rising and falling edge deglitch circuit reduce the likelihood

of shutting the device down due to noise on VIN.

SLOW-START/ENABLE (SS/ENA)

The slow-start/enable pin provides two functions. First, the

pin acts as an enable (shutdown) control by keeping the

device turned off until the voltage exceeds the start

threshold voltage of approximately 1.2 V. When SS/ENA

exceeds the enable threshold, device start-up begins. The

reference voltage fed to the error amplifier is linearly

ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the

converter output voltage reaches regulation in

approximately 3.35 ms. Voltage hysteresis and a 2.5-µs

falling edge deglitch circuit reduce the likelihood of

triggering the enable due to noise.

The second function of the SS/ENA pin provides an

external means of extending the slow-start time with a

low-value capacitor connected between SS/ENA and

AGND.

Adding a capacitor to the SS/ENA pin has two effects on

start-up. First, a delay occurs between release of the

SS/ENA pin and start-up of the output. The delay is

proportional to the slow-start capacitor value and lasts

until the SS/ENA pin reaches the enable threshold. The

start-up delay is approximately:

td + C(SS)

1.2 V

5 mA

Second, as the output becomes active, a brief ramp-up at

the internal slow-start rate may be observed before the

externally set slow-start rate takes control and the output

rises at a rate proportional to the slow-start capacitor. The

slow-start time set by the capacitor is approximately:

t(SS) + C(SS)

0.7 V

5 mA

The actual slow-start time is likely to be less than the above

approximation due to the brief ramp-up at the internal rate.

The low side MOSFET is off during the slow-start

sequence.

VBIAS REGULATOR (VBIAS)

The VBIAS regulator provides internal analog and digital

blocks with a stable supply voltage over variations in

junction temperature and input voltage. A high quality,

low-ESR, ceramic bypass capacitor is required on the

VBIAS pin. X7R or X5R grade dielectrics are

recommended because their values are more stable over

temperature. The bypass capacitor must be placed close

to the VBIAS pin and returned to AGND.

External loading on VBIAS is allowed, with the caution that

internal circuits require a minimum VBIAS of 2.70 V, and

external loads on VBIAS with ac or digital switching noise

may degrade performance. The VBIAS pin may be useful

as a reference voltage for external circuits.

VOLTAGE REFERENCE

The voltage reference system produces a precise Vref

signal by scaling the output of a temperature stable

bandgap circuit. During manufacture, the bandgap and

scaling circuits are trimmed to produce 0.891 V at the

output of the error amplifier, with the amplifier connected

as a voltage follower. The trim procedure adds to the high

precision regulation of the TPS54873, since it cancels

offset errors in the scale and error amplifier circuits.

OSCILLATOR AND PWM RAMP

The oscillator frequency can be set to internally fixed

values of 350 kHz or 550 kHz using the SYNC pin as a

static digital input. If a different frequency of operation is

required for the application, the oscillator frequency can be

externally adjusted from 280 to 700 kHz by connecting a

resistor between the RT pin and AGND and floating the

SYNC pin. The switching frequency is approximated by

the following equation, where R is the resistance from RT

to AGND:

(2)

(3)

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