GL3522-22 Datasheet

© 2014 Genesys Logic, Inc. - All rights reserved.

Page 4

GLI Confidential

Table of Contents

CHAPTER 1

GENERAL DESCRIPTION....................................................................... 7

CHAPTER 2

FEATURES .................................................................................................. 8

CHAPTER 3

PIN ASSIGNMENT................................................................................... 10

3.1 Pinout............................................................................................................................ 10

3.2 Pin Descriptions ........................................................................................................... 12

CHAPTER 4

FUNCTION DESCRIPTION ................................................................... 15

4.1 Block Diagram ............................................................................................................. 15

4.2 General Description..................................................................................................... 16

4.2.1 USB 2.0 USPORT Transceiver........................................................................... 16

4.2.2 USB 3.0 USPORT Transceiver........................................................................... 16

4.2.3 PLL (Phase Lock Loop) ...................................................................................... 16

4.2.4 Regulator .............................................................................................................. 16

4.2.5 SPI Engine ............................................................................................................ 16

4.2.6 RAM/ROM/CPU ................................................................................................. 16

4.2.7 UTMI (USB 2.0 Transceiver Microcell Interface)............................................ 16

4.2.8 SIE (Serial Interface Engine).............................................................................. 16

4.2.9 Control/Status Register ....................................................................................... 16

4.2.10 Power Management Engine.............................................................................. 16

4.2.11 Router/Aggregator Engine................................................................................ 17

4.2.12 REPEATER ....................................................................................................... 17

4.2.13 TT ........................................................................................................................ 17

4.2.14 CDP Control Logic ............................................................................................ 18

4.2.15 USB 3.0/USB 2.0 DSPORT Transceiver .......................................................... 18

4.3 Configuration and I/O Settings .................................................................................. 19

4.3.1 RESET Setting ..................................................................................................... 19

4.3.2 PGANG Setting.................................................................................................... 20

4.3.3 SELF/BUS Power Setting ................................................................................... 21

4.3.4 LED Connections ................................................................................................. 21

4.3.5 Power Switch Enable Polarity ............................................................................ 21

4.3.6 Port Number Configuration ............................................................................... 22