HIP2100

FN4022 Rev.16.00

Page 6 of 14

Aug 8, 2019

BOOT STRAP DIODE

Low-Current Forward Voltage

VDL

IVDD-HB = 100µA

-

0.45 0.55

-

0.7

V

High-Current Forward Voltage

VDH

IVDD-HB = 100mA

-

0.7

0.8

-

1

V

Dynamic Resistance

RD

IVDD-HB = 100mA

-

0.8

1

-

1.5

Ω

LO GATE DRIVER

Low Level Output Voltage

VOLL

ILO = 100mA

-

0.25

0.3

-

0.4

V

High Level Output Voltage

VOHL

ILO = -100mA, VOHL = VDD-VLO

-

0.25

0.3

-

0.4

V

Peak Pullup Current

IOHL

VLO = 0V

-

2

-

-

-

A

Peak Pulldown Current

IOLL

VLO = 12V

-

2

-

-

-

A

HO GATE DRIVER

Low Level Output Voltage

VOLH

IHO = 100mA

-

0.25

0.3

-

0.4

V

High Level Output Voltage

VOHH

IHO = -100mA, VOHH = VHB-VHO

-

0.25

0.3

-

0.4

V

Peak Pullup Current

IOHH

VHO = 0V

-

2

-

-

-

A

Peak Pulldown Current

IOLH

VHO = 12V

-

2

-

-

-

A

Electrical Specifications

VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, unless otherwise specified. (Continued)

PARAMETERS

SYMBOL

TEST CONDITIONS

TJ = +25°C

TJ = -40°C TO +125°C

UNIT

MIN TYP MAX

MIN

(Note 8)

MAX

(Note 8)

Switching Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, unless otherwise specified.

PARAMETERS

SYMBOL

TEST

CONDITIONS

TJ = +25°C

TJ = -40°C TO +125°C

UNIT

MIN TYP MAX

MIN

(Note 8)

MAX

(Note 8)

Lower Turn-Off Propagation Delay (LI Falling to LO Falling)

tLPHL

-

20

35

-

45

ns

Upper Turn-Off Propagation Delay (HI Falling to HO Falling)

tHPHL

-

20

35

-

45

ns

Lower Turn-On Propagation Delay (LI Rising to LO Rising)

tLPLH

-

20

35

-

45

ns

Upper Turn-On Propagation Delay (HI Rising to HO Rising)

tHPLH

-

20

35

-

45

ns

Delay Matching: Lower Turn-On and Upper Turn-Off

tMON

-

2

8

-

10

ns

Delay Matching: Lower Turn-Off and Upper Turn-On

tMOFF

-

2

8

-

10

ns

Either Output Rise/Fall Time

tRC, tFC

CL = 1000pF

-

10

-

-

-

ns

Either Output Rise/Fall Time (3V to 9V)

tR, tF

CL = 0.1µF

-

0.5

0.6

-

0.8

µs

Either Output Rise Time Driving DMOS

tRD

CL = IRFR120

-

20

-

-

-

ns

Either Output Fall Time Driving DMOS

tFD

CL = IRFR120

-

10

-

-

-

ns

Minimum Input Pulse Width that Changes the Output

tPW

-

-

-

-

50

ns

Bootstrap Diode Turn-On or Turn-Off Time

tBS

-10

-

-

-

ns

NOTE:

8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.