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PCT2075DP датащи(PDF) 7 Page - NXP Semiconductors

номер детали PCT2075DP
подробное описание детали  I2C-bus Fm, 1 degree C accuracy, digital temperature sensor and thermal watchdog
PDF  37 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCT2075DP датащи(HTML) 7 Page - NXP Semiconductors

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PCT2075
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 9.1 — 21 April 2017
7 of 37
NXP Semiconductors
PCT2075
I2C-bus Fm+ digital temperature sensor and thermal watchdog
In both cases, comparator mode and interrupt mode, the OS output is activated only if a
number of consecutive faults, defined by the device fault queue, has been met. The fault
queue is programmable and stored in the two bits, B3 and B4, of the Configuration
register. Also, the OS output active state is selectable as HIGH or LOW by setting
accordingly the configuration register bit B2.
At power-up, the PCT2075 is put into normal operation mode in OS comparator mode, the
Tots is set to 80 C, the Thys is set to 75 C, the OS active state is selected LOW and the
fault queue is equal to 1. The temp reading data is 0
C and not updated until the first
conversion is completed in about 28 ms. The default Tots and Thys is set at the factory and
can be modified on custom part number.
The OS response to the temperature is illustrated in Figure 7.
7.2 I2C-bus serial interface
The device can be connected to a compatible 2-wire serial interface Fast-mode Plus
I2C-bus as a slave device under the control of a controller or master device, using two
device terminals, SCL and SDA. The controller must provide the SCL clock signal and
write/read data to/from the device through the SDA terminal. Notice that if the I2C-bus
common pull-up resistors have not been installed as required for I2C-bus, then an external
pull-up resistor, about 1.5 k
, is needed for each of these two terminals. The bus
communication protocols are described in Section 7.10.
(1) OS is reset by either reading register or putting the device in shutdown mode. It is assumed that
the fault queue is met at each Tots and Thys crossing point.
Fig 7.
OS response to temperature
002aah455
(1)
(1)
(1)
Tots
Thys
OS reset
OS active
OS reset
OS active
OS output in comparator mode
OS output in interrupt mode
reading temperature limits



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