SN54173, SN54LS173A, SN74173, SN74LS173A

4-BIT D-TYPE REGISTERS

WITH 3-STATE OUTPUTS

SDLS067A – OCTOBER 1976 – REVISED JUNE 1999

6

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

switching characteristics, VCC = 5 V, TA = 25°C, RL = 400 Ω (see Figure 1)

PARAMETER

TEST CONDITIONS

SN54173

SN74173

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

fmax

Maximum clock frequency

25

35

25

35

MHz

tPHL

Propagation delay time,

high-to-low-level output from clear input

18

27

18

27

ns

tPLH

Propagation delay time,

low-to-high-level output from clock input

CL = 50 pF

28

43

28

43

ns

tPHL

Propagation delay time,

high-to-low-level output from clock input

L

19

31

19

31

ns

tPZH

Output enable time to high level

7

16

30

7

16

30

ns

tPZL

Output enable time to low level

7

21

30

7

21

30

ns

tPHZ

Output disable time from high level

CL =5 pF

3

5

14

3

5

14

ns

tPLZ

Output disable time from low level

CL = 5 pF

3

11

20

3

11

20

ns