MSP430G2231-Q1

SLAS787B – NOVEMBER 2011 – REVISED MARCH 2014

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7.3 Terminal Functions

Table 2. Terminal Functions

TERMINAL

NO.

I/O

DESCRIPTION

NAME

PW

RSA

P1.0/

General-purpose digital I/O pin

TA0CLK/

Timer0_A, clock signal TACLK input

2

1

I/O

ACLK/

ACLK signal output

A0

ADC10 analog input A0

P1.1/

General-purpose digital I/O pin

TA0.0/

3

2

I/O

Timer0_A, capture: CCI0A input, compare: Out0 output

A1

ADC10 analog input A1

P1.2/

General-purpose digital I/O pin

TA0.1/

4

3

I/O

Timer0_A, capture: CCI1A input, compare: Out1 output

A2

ADC10 analog input A2

P1.3/

General-purpose digital I/O pin

ADC10CLK/

ADC10, conversion clock output

5

4

I/O

A3/

ADC10 analog input A3

VREF-/VEREF

ADC10 negative reference voltage

P1.4/

General-purpose digital I/O pin

SMCLK/

SMCLK signal output

A4/

6

5

I/O

ADC10 analog input A4

VREF+/VEREF+/

ADC10 positive reference voltage

TCK

JTAG test clock, input terminal for device programming and test

P1.5/

General-purpose digital I/O pin

TA0.0/

Timer0_A, compare: Out0 output

A5/

7

6

I/O

ADC10 analog input A5

SCLK/

USI: clock input in I2C mode; clock input/output in SPI mode

TMS

JTAG test mode select, input terminal for device programming and test

P1.6/

General-purpose digital I/O pin

TA0.1/

Timer0_A, capture: CCI1A input, compare: Out1 output

A6/

ADC10 analog input A6

8

7

I/O

SDO/

USI: Data output in SPI mode

SCL/

USI: I2C clock in I2C mode

TDI/TCLK

JTAG test data input or test clock input during programming and test

P1.7/

General-purpose digital I/O pin

A7/

ADC10 analog input A7

SDI/

9

8

I/O

USI: Data input in SPI mode

SDA/

USI: I2C data in I2C mode

TDO/TDI(1)

JTAG test data output terminal or test data input during programming and test

XIN/

Input terminal of crystal oscillator

P2.6/

13

12

I/O

General-purpose digital I/O pin

TA0.1

Timer0_A, compare: Out1 output

XOUT/

Output terminal of crystal oscillator(2)

12

11

I/O

P2.7

General-purpose digital I/O pin

RST/

Reset

NMI/

10

9

I

Nonmaskable interrupt input

SBWTDIO

Spy-Bi-Wire test data input/output during programming and test

TEST/

Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST.

11

10

I

SBWTCK

Spy-Bi-Wire test clock input during programming and test

DVCC

1

15, 16

NA

Supply voltage

DVSS

14

13, 14

NA

Ground reference

QFN Pad

-

Pad

NA

QFN package pad connection to VSS recommended.

(1)

TDO or TDI is selected via JTAG instruction.

(2)

If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to

this pad after reset.

6

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