MSP430G2231-Q1

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SLAS787B – NOVEMBER 2011 – REVISED MARCH 2014

8.4 Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h.

The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed) the

CPU goes into LPM4 immediately after power-up.

Table 5. Interrupt Sources, Flags, and Vectors

SYSTEM

WORD

INTERRUPT SOURCE

INTERRUPT FLAG

PRIORITY

INTERRUPT

ADDRESS

Power-Up

PORIFG

External Reset

RSTIFG

Watchdog Timer+

WDTIFG

Reset

0FFFEh

31, highest

Flash key violation

KEYV(2)

PC out-of-range(1)

NMI

NMIIFG

(non)-maskable

Oscillator fault

OFIFG

(non)-maskable

0FFFCh

30

Flash memory access violation

ACCVIFG(2)(3)

(non)-maskable

0FFFAh

29

0FFF8h

28

0FFF6h

27

Watchdog Timer+

WDTIFG

maskable

0FFF4h

26

Timer_A2

TACCR0 CCIFG(4)

maskable

0FFF2h

25

Timer_A2

TACCR1 CCIFG, TAIFG(2)(4)

maskable

0FFF0h

24

0FFEEh

23

0FFECh

22

ADC10

ADC10IFG(4)(5)

maskable

0FFEAh

21

USI

USIIFG, USISTTIFG(2)(4)

maskable

0FFE8h

20

I/O Port P2 (two flags)

P2IFG.6 to P2IFG.7(2)(4)

maskable

0FFE6h

19

I/O Port P1 (eight flags)

P1IFG.0 to P1IFG.7(2)(4)

maskable

0FFE4h

18

0FFE2h

17

0FFE0h

16

See (6)

0FFDEh to

15 to 0, lowest

0FFC0h

(1)

A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from

within unused address ranges.

(2)

Multiple source flags

(3)

(non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.

(4)

Interrupt flags are located in the module.

(5)

MSP430G2x31 only

(6)

The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if

necessary.

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