10 Layout

10.1 Layout Guidelines

• Decoupling caps should be placed next to each power terminal on the HD3SS212. Take care to minimize the

stub length of the race connecting the capacitor to the power pin.

• Avoid sharing vias between multiple decoupling caps

• Place vias as close as possible to the decoupling cop solder pad

• Widen VDD/GND planes to reduce effect if static and dynamic IR drop

• The VBUS traces/planes must be wide enough to carry maximum of 2-A current

10.2 Layout Example

VDD3P3

GND

SEL

VBUS

VDD3P3

VSS

AX+

AX-

BX+

BX-

CX+

CX-

Use controlled-impedance

Transmission media for all

Differential signals

3.3V Logic level

VBUS traces wide

enough to carry 2A

current

Figure 10-1. Layout Example

HD3SS212

SLAS822D – DECEMBER 2011 – REVISED DECEMBER 2020

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