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Resistor

String DAC

Powerdown

Circuitry

VOUT

Amplifier

Resistor

Network

CURRENT CONSUMPTION

DAC6573

SLAS402 – NOVEMBER 2003

Table 8. Power-Down Modes of Operation for the DAC6573

CTRL[0]

MSB[7]

MSB[6]

OPERATING MODE

1

0

0

PWD, high impedance DAC output

1

0

1

PWD, 1 k

Ω to GND DAC ouptut

1

1

0

PWD, 100 k

Ω to GND DAC output

1

1

1

PWD, high impedance DAC output

When (CTRL[0] = PD0 = 0), the device works normally with its normal power consumption of 150 µA at 5 V per

channel. However, for the power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not only

does the supply current fall but also the output stage is also internally switched from the output of the amplifier to

a resistor network of known values. This has the advantage that the output impedance of the device is known

while in power-down mode. There are three different options: The output is connected internally to GND through

a 1 k

Ω resistor, a 100 kΩ resistor or left open-circuit (high impedance). The output stage is illustrated in

Figure 37.

Figure 37. Output Stage During Power Down

All linear circuitry is shut down when the power-down mode is activated. However, the contents of the DAC

register are unaffected when in power-down. The time to exit power down is typically 2.5 µs for VDD = 5 V and 5

µs for VDD = 3 V. (See the Typical Curves section for additional information.)

The DAC6573 offers a flexible power-down interface based on channel register operation. A channel consists of

a single 10-bit DAC with power-down circuitry, a temporary storage register (TR) and a DAC register (DR). TR

and DR are both 12 bits wide. Two MSBs represent the power-down condition and the 10 LSBs represent data

for TR and DR. By using bits 11 and 10 of TR and DR, a power-down condition can be temporarily stored and

used just like data. Internal circuits ensure that MSB[7] and MSB[6] get transferred to TR[11] and TR[10] (DR[11]

and DR[10]) when the power-down flag (CTRL[0] = PD0) is set. Therefore, DAC6573 treats power-down

conditions like data and all the operational modes are still valid for power down. It is possible to broadcast a

power-down condition to all the DAC6573s in the system, or it is possible to simultaneously power down a

channel while updating data on other channels.

The DAC6573 typically consumes 150 µA at VDD = 5 V and 125 µA at VDD = 3 V for each active channel,

including reference current consumption. Additional current consumption can occur at the digital inputs if VIH <<

VDD. For most efficient power operation, CMOS logic levels are recommended at the digital inputs to the DAC. In

power-down mode, typical current consumption is 200 nA.

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