XI

VSSOSC

XO

CL1

CL2

Crystal

13

TUSB9261

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SLLSE67I – MARCH 2011 – REVISED MARCH 2016

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7.3.2 Clock Connections

7.3.2.1 Clock Source Requirements

The TUSB9261 supports an external oscillator source or a crystal unit. If a clock is provided to XI instead of a

crystal, XO is left open and VSSOSC should be connected to the PCB ground plane. Otherwise, if a crystal is

used, the connection needs to follow these guidelines.

Because XI and XO are coupled to other leads and supplies on the PCB, it is important to keep them as short as

possible and away from any switching leads. TI also recommends to minimize the capacitance between XI and

XO. This can be accomplished by connecting the VSSOSC lead to the two external capacitors CL1 and CL2 and

shielding them with the clean ground lines. The VSSOSC should not be connected to PCB ground when using a

crystal.

Load capacitance (Cload) of the crystal (varies with the crystal vendor) is the total capacitance value of the entire

oscillation circuit system as seen from the crystal. It includes two external capacitors, CL1 and CL2, in Figure 1.

The trace length between the decoupling capacitors and the corresponding power pins on the TUSB9261 must

be minimized. TI also recommends that the trace length from the capacitor pad to the power or ground plane be

minimized.

Figure 1. Typical Crystal Connections

7.3.2.2 Clock Source Selection Guide

Reference clock jitter is an important parameter. Jitter on the reference clock degrades both the transmit eye and

receiver jitter tolerance no matter how clean the rest of the PLL is, thereby impairing system performance.

Additionally, a particularly jittery reference clock may interfere with the PLL lock detection mechanism, forcing the

lock detector to issue an Unlock signal. A good-quality, low-jitter reference clock is required to achieve

compliance with supported USB3.0 standards. For example, USB3.0 specification requires the random jitter (RJ)

component of either RX or TX to be 2.42 ps (random phase jitter calculated after applying jitter transfer function

(JTF)). As the PLL typically has a number of additional jitter components, the reference clock jitter must be

considerably below the overall jitter budget.

7.4 Device Functional Modes

7.4.1 VBUS Power

Power can be supplied by a USB cable on the terminal VBUS. When using power from VBUS, both the

TUSB9261 and the SATA device are allowed to draw only up to 500 mA from VBUS when operating.

7.4.2 External Power

Power can be supplied from an external power source. When using an external power source, both the

TUSB9261 and the SATA interface can draw all their current from the external supply.