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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ZL40264 датащи(PDF) 21 Page - Microchip Technology |
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ZL40264 датащи(HTML) 21 Page - Microchip Technology |
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21 / 36 page  2024 Microchip Technology Inc. DS20006788A-page 21 ZL40264 Additive Jitter as per PCIe 3.0 (PLL_BW = 2 MHz to 5 MHz, CDR = 10 MHz) TPCIe_3.0 — 33 41 fs RMS Input clock: 100 MHz Additive Jitter as per PCIe 4.0 (PLL_BW = 2 MHz to 5 MHz, CDR = 10 MHz) TPCIe_4.0 — 33 41 fs RMS Input clock: 100 MHz Additive Jitter as per PCIe 5.0 (PLL_BW = 0.5 MHz to 1.8 MHz, CDR for 32 GT/s CC) TPCIe_5.0 — 13 16 fs RMS Input clock: 100 MHz Additive Jitter as per PCIe 6.0 (PLL_BW = 0.5 MHz to 1 MHz, CDR for 64 GT/s CC) TPCIe_6.0 — 8 10 fs RMS Input clock: 100 MHz Additive Jitter as per Intel QPI 9.6 Gbps TPCIe — 61 75 fs RMS Input clock: 100 MHz Additive RMS Jitter in 1 MHz to 20 MHz Band Tj_1M_20M —87 106 fs RMS Input clock: 100 MHz — 56 68 Input clock: 133 MHz — 26 34 Input clock: 400 MHz — 25 32 Input clock: 491.52 MHz Additive RMS Jitter in 12 kHz to 20 MHz Band Tj_12k_20M —91 112 fs RMS Input clock: 100 MHz — 60 75 Input clock: 133 MHz — 32 48 Input clock: 400 MHz — 30 43 Input clock: 491.52 MHz Noise Floor NF — –161 –159 dBc/Hz Input clock: 100 MHz — –162 –161 Input clock: 133 MHz — –160 –157 Input clock: 400 MHz — –158 –155 Input clock: 491.52 MHz Note 1: Values are over recommended operating conditions. TABLE 3-9: HCSL OUTPUTS FOR VDDO = 2.5V Note 1 Parameter Symbol Min Typ. Max Units Condition Rising edge rate rise_rate 1.3 1.6 1.9 V/ns Note 2, Note 3 Falling edge rate fall_rate 1.3 1.6 1.9 Vms Note 2, Note 3 Differential high voltage VIH 0.6 — 0.9 V Note 2 Differential low voltage VIL –0.9 — –0.6 V Note 2 Single-ended high voltage VSIH 0.58 0.71 0.84 V DC measurement Single-ended low voltage VSIL –0.01 0 0.01 V DC measurement Absolute crossing voltage VCROSS 0.25 0.31 0.37 V Note 1, Note 4, Note 5 Variation of VCROSS over all rising clock edges ∆VCROSS 0.04 0.05 0.06 V Note 1, Note 4, Note 9 Ring back voltage margin VRB 0.514 0.660 0.791 V Note 2, Note 11 Time before VRB is allowed tSTABLE 4.6 — — ns Note 2, Note 11 Additive cycle-to-cycle jitter TJCC —5.5 7.1 ps peak- to-peak Note 2 Absolute maximum voltage VMAX — — 0.90 Note 1, Note 7 Absolute minimum voltage VMIN –0.05 — — Note 1, Note 8 Output duty-cycle (when input has 50% duty-cycle) duty_cycle 48 50 52 % Note 2 TABLE 3-8: HCSL (PCIE) JITTER PERFORMANCE FOR VDDO = 3.3V (CONTINUED) |
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