UCC29421, UCC29422, UCC39421, UCC39422

MULTIMODE HIGHFREQUENCY PWM CONTROLLER

SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005

9

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

low power mode

During normal operation, at medium to high load currents, the switching frequency remains fixed, programmed

by the resistor on the RT pin. At these higher loads, the gate drive output on the CHRG pin (for the N-channel

charge FET) is the higher of VIN or VPUMP. When the load current drops (sensed by a drop in the error amp

voltage), the UCC39421 automatically enters LP mode, and the gate drive voltage on the CHRG pin is reduced

to lower gate drive losses. This helps to maintain high efficiency at light loads where the gate drive losses begin

to dominate and the lowest possible Rds(on) is not required. If the load increases, normal or “high power” mode

resumes. The expression for gate drive power loss is given by equation (1). It can be seen that the power varies

as a function of the applied gate voltage squared.

P

GATELOSS +

Q

G

V

G

2

f

V

S

(1)

Where QG is the total gate charge and VS is the gate voltage specified in the MOSFET manufacturer’s data

sheet, VG is the applied gate drive voltage, and f is the switching frequency.

The nominal COMP voltage where LP mode is entered is 0.6 V. Given the internal offset and gain of the

current-sense amplifier, this corresponds to a peak switch current of:

I

PEAK +

(0.6

* 0.3)

K

R

SENSE

+

0.03

R

SENSE

(2)

Where 0.6 V is the threshold for LP mode, 0.3 V is the internal offset, K is the nominal current-sense amplifier

gain of 10, and RSENSE is the value of the current-sense resistor. If the peak inductor current is below this value,

the UCC39421 enters LP mode and the gate drive voltage on the CHRG pin is equal to VIN. At peak currents

higher than this, the gate drive voltage is the higher of VIN or VPUMP.

PFM mode

At very light loads, the UCC39421 enters PFM mode. In this mode, when the error amplifier output voltage drops

below the PFM threshold, the controller goes into sleep mode until VOUT has dropped slightly (30 mV measured

at the feedback pin). At this time, the controller turns back on and operates at fixed frequency for a short duration

(typically a few hundred microseconds) until the output voltage has increased and the error amplifier output

voltage has dropped below the PFM threshold once again. Then the converter turns off and the cycle repeats.

This results in a very low duty cycle of operation, reducing all losses and greatly improving light load efficiency.

During sleep mode, most of the circuitry internal to the UCC39421 is powered down, reducing quiescent current

and maximizing efficiency.

The peak inductor current at which this mode is entered is user programmable by setting the voltage on the PFM

pin. This can be done with a single resistor in series with the feedback divider, as shown in the application

diagrams. The nominal peak current threshold for PFM mode is defined by the equation:

I

PEAK ^

1.25

R1

R1

)R2

* 0.3

K

R

SENSE

(3)