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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AFE5803ZCF датащи(PDF) 4 Page - Texas Instruments |
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AFE5803ZCF датащи(HTML) 4 Page - Texas Instruments |
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4 / 53 page  AFE5803 SLOS763A – JANUARY 2012 – REVISED JANUARY 2012 www.ti.com DEVICE INFORMATION PIN CONFIGURATION Top View ZCF (BGA-135) 1 2 3 4 5 6 7 8 9 A AVDD INP8 INP7 INP6 INP5 INP4 INP3 INP2 INP1 B CM_BYP ACT8 ACT7 ACT6 ACT5 ACT4 ACT3 ACT2 ACT1 C AVSS INM8 INM7 INM6 INM5 INM4 INM3 INM2 INM1 D AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVDD AVDD E CH7_TEST_OUTP CH7_TEST_OUTM AVSS AVSS AVSS AVSS AVSS AVDD AVDD F CH7_BUFFER_OUTM CH7_BUFFER_OUTP AVSS AVSS AVSS AVSS AVSS DNC DNC G AVSS AVSS AVSS AVSS AVSS AVSS AVSS DNC DNC H CH8_BUFFER_OUTM CH8_BUFFER_OUTP AVSS AVSS AVSS AVSS AVSS PDN_GLOBAL RESET J CH8_TEST_OUTP CH8_TEST_OUTM AVSS AVSS AVSS AVDD_ADC AVDD_ADC PDN_VCA SCLK K AVDD AVDD_5V VCNTLP VCNTLM VHIGH AVSS DNC AVDD_ADC SDATA L CLKP_ADC CLKM_ADC AVDD_ADC REFM DNC DNC DNC PDN_ADC SEN M AVDD_ADC AVDD_ADC VREF_IN REFP DNC DNC DNC DNC SDOUT N D8P D8M DVDD DNC DVSS DNC DVDD D1M D1P P D7M D6M D5M FCLKM DVSS DCLKM D4M D3M D2M R D7P D6P D5P FCLKP DVSS DCLKP D4P D3P D2P PIN FUNCTIONS PIN DESCRIPTION NO. NAME B9~ B2 ACT1...ACT8 Active termination input pins for CH1~8. 1 μF capacitors are recommended. See the Applicaiton Information section. A1, D8, D9, E8, AVDD 3.3 V Analog supply for LNA, VCAT, PGA, LPF blocks. E9, K1 K2 AVDD_5V 5 V Analog supply for LNA, VCAT, PGA, LPF blocks. J6, J7, K8, L3, AVDD_ADC 1.8 V Analog power supply for ADC. M1, M2 C1, D1~D7, E3~E7, F3~F7, G1~G7, AVSS Analog ground. H3~H7,J3~J5, K6 Negative input of differential ADC clock. In the single-end clock mode, it can be tied to GND directly or L2 CLKM_ADC through a 0.1 µF capacitor. Positive input of differential ADC clock. In the single-end clock mode, it can be tied to clock signal L1 CLKP_ADC directly or through a 0.1 µF capacitor. Bias voltage and bypass to ground. ≥1µF is recommended. To suppress the ultra low frequency noise, B1 CM_BYP 10 µF can be used. E2 CH7_TEST_OUTM CH7 PGA negative output when PGA test mode is enabled. Can be floated if not used. E1 CH7_TEST_OUTP CH7 PGA positive output when PGA test mode is enabled. Can be floated if not used. Negative differential output for the buffer amplifier when PGA test mode is enabled. Can be floated if not F1 CH7_BUFFER_OUTM used. See the TEST MODES in the application information section. Positive differential output for the buffer amplifier when PGA test mode is enabled. Can be floated if not F2 CH7_BUFFER_OUTP used. See the TEST MODES in the application information section. J2 CH8_TEST_OUTM CH8 PGA negative output when PGA test mode is enabled. Can be floated if not used. J1 CH8_TEST_OUTP CH8 PGA positive output when PGA test mode is enabled. Can be floated if not used. Negative differential output for the buffer amplifier when PGA test mode is enabled. Can be floated if not H1 CH8_BUFFER_OUTM used. See the TEST MODES in the application information section. Positive differential output for the buffer amplifier when PGA test mode is enabled. Can be floated if not H2 CH8_BUFFER_OUTP used. See the TEST MODES in the application information section. N8, P9~P7, D1M~D8M ADC CH1~8 LVDS negative outputs P3~P1, N2 N9, R9~R7, D1P~D8P ADC CH1~8 LVDS positive outputs R3~R1, N1 P6 DCLKM LVDS bit clock (7x) negative output 4 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): AFE5803 |
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