ADC12DL080

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SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013

Using an inadequate amplifier to drive the analog input. As explained in Signal Inputs, the capacitance seen

at the input alternates between 8 pF and 7 pF, depending upon the phase of the clock. This dynamic load is

more difficult to drive than is a fixed capacitance. If the amplifier exhibits overshoot, ringing, or any evidence of

instability, even at a very low level, it will degrade performance. A small series resistor at each amplifier output

and a capacitor at the analog inputs (as shown in Figure 44) will improve performance.

Also, it is important that the signals at the two inputs have exactly the same amplitude and be exactly 180º out of

phase with each other. Board layout, especially equality of the length of the two traces to the input pins, will

affect the effective phase between these two signals. Remember that an operational amplifier operated in the

non-inverting configuration will exhibit more time delay than will the same device operating in the inverting

configuration.

Operating with the reference pins outside of the specified range. As mentioned in Reference Pins, VREF

should be in the range of

0.8V

≤ VREF ≤ 1.2V

(7)

Operating outside of these limits could lead to performance degradation.

Inadequate network on Reference Bypass pins (VRPA, VRNA, VRMA, VRPB, VRNB and VRMB). As mentioned in

Reference Pins, these pins should be bypassed with 0.1 µF capacitors to ground at VRMA and VRMB and with a

10 µF between pins VRPA and VRNA and between VRPB and VRNB for best performance.

Using a clock source with excessive jitter, using excessively long clock signal trace, or having other

signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive

output noise and a reduction in SNR and SINAD performance.

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