ADC12DL080

SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013

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OF/DOEN, OEA/OF, and OEB/DRDY

OF/DOEN (pin 21) selects the output format (OF) or enables the DRDY output (DOEN). The state of this pin also

controls the function of pins 22 (OEA/OF) and 41 (OEB/DRDY).

When OF/DOEN is tied to VRMA or VRMB, DRDY is enabled. Pin 41 is used as the DRDY output strobe, and pin

22 is used to select the output format. Output Enable for channels A and B are not available in this mode.

When OF/DOEN is LOW, the output data format is offset binary. With OF/DOEN tied HIGH, the output format is

2's complement.

The following table describes the function of these pins.

Table 4. OF/DOEN, OEA/OF, OEB/DRDY Pin Functions

Pin 21 State

Pin 21 Function

Pin 22 Function

Pin 41 Function

VRMA or VRMB

DRDY output is enabled

Output Format

DRDY Output

LOW = Offset Binary

HIGH = 2's Complement

Logic LOW

Output Format = Offset Binary

Output Enable for Channel A

Output Enable for Channel B

LOW = outputs are enabled

LOW = outputs are enabled

Logic HIGH

Output Format = 2's Complement

HIGH = outputs are in high

HIGH = outputs are in high

impedance state

impedance state

PD

The PD pin, when high, holds the ADC12DL080 in a power-down mode to conserve power when the converter is

not being used. The output data pins are undefined and the data in the pipeline is corrupted while in the power

down mode.

The Power Down Mode Exit Cycle time is determined by the value of the components on pins 4, 5, 6, 12, 13 and

14. These capacitors loose their charge in the Power Down mode and must be recharged by on-chip circuitry

before conversions can be accurate. Smaller capacitor values allow slightly faster recovery from the power down

mode, but can result in a reduction in SNR, SINAD and ENOB performance.

OUTPUTS

The ADC12DL080 has 12 TTL/CMOS compatible Data Output pins for each output. Valid data is present at

these outputs while the OE and PD pins are low. Be very careful when driving a high capacitance bus. The more

capacitance the output drivers must charge for each conversion, the more instantaneous digital current flows

through VDR and DR GND. These large charging current spikes can cause on-chip ground noise and couple into

the analog circuitry, degrading dynamic performance. Adequate bypassing, limiting output capacitance and

careful attention to the ground plane will reduce this problem. Additionally, bus capacitance beyond the specified

10 pF/pin will cause tOD to increase, making it difficult to properly latch the ADC output data. The result could be

an apparent reduction in dynamic performance.

To minimize noise due to output switching, minimize the load currents at the digital outputs. This can be done by

connecting buffers (74LVTH162374, for example) between the ADC outputs and any other circuitry. Only one

driven input should be connected to each output pin. Additionally, inserting series resistors of about 100

Ω at the

digital outputs, close to the ADC pins, will isolate the outputs from trace and other circuit capacitances and limit

the output currents, which could otherwise result in performance degradation. See Figure 43.

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