GND

VA

ADC08060

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SNAS120H – OCTOBER 2000 – REVISED MARCH 2013

PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS

Pin No.

Symbol

Equivalent Circuit

Description

6

VIN

Analog signal input. Conversion range is VRB to VRT.

Analog Input that is the high (top) side of the reference ladder

of the ADC. Nominal range is 1.0V to VA. Voltage on VRT and

3

VRT

VRB inputs define the VIN conversion range. Bypass well. See

THE ANALOG INPUT for more information.

Mid-point of the reference ladder. This pin should be bypassed

9

VRM

to a clean, quiet point in the analog ground plane with a 0.1

µF capacitor.

Analog Input that is the low side (bottom) of the reference

ladder of the ADC. Nominal range is 0.0V to (VRT – 1.0V).

10

VRB

Voltage on VRT and VRB inputs define the VIN conversion

range. Bypass well. See THE ANALOG INPUT for more

information.

Power Down input. When this pin is high, the converter is in

23

PD

the Power Down mode and the data output pins hold the last

conversion result.

CMOS/TTL compatible digital clock Input. VIN is sampled on

24

CLK

the falling edge of CLK input.

13 thru 16

Conversion data digital Output pins. D0 is the LSB, D7 is the

and

D0–D7

MSB. Valid data is output just after the rising edge of the CLK

19 thru 22

input.

7

VIN GND

Reference ground for the single-ended analog input, VIN.

Positive analog supply pin. Connect to a clean, quiet voltage

source of +3V. VA should be bypassed with a 0.1 µF ceramic

1, 4, 12

VA

chip capacitor for each pin, plus one 10 µF capacitor. See

POWER SUPPLY CONSIDERATIONS for more information.

Power supply for the output drivers. If connected to VA,

18

DR VD

decouple well from VA.

17

DR GND

The ground return for the output driver supply.

2, 5, 8, 11

AGND

The ground return for the analog supply.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

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