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ST72321B датащи(PDF) 24 Page - STMicroelectronics

номер детали ST72321B
подробное описание детали  64/44-pin 8-bit MCU with 32 to 60K Flash/ROM, ADC, five timers, SPI, SCI, I2C interface
PDF  187 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72321B датащи(HTML) 24 Page - STMicroelectronics

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6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and re-
ducing the number of external components. An
overview is shown in Figure 12.
For more details, refer to dedicated parametric
section.
Main features
■ Optional PLL for multiplying the frequency by 2
(not to be used with internal RC oscillator)
■ Reset Sequence Manager (RSM)
■ Multi-Oscillator Clock Management (MO)
– 5 Crystal/Ceramic resonator oscillators
– 1 Internal RC oscillator
■ System Integrity Management (SI)
– Main supply Low voltage detection (LVD)
– Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supply or
the EVD pin
6.1 PHASE LOCKED LOOP
If the clock frequency input to the PLL is in the
range 2 to 4 MHz, the PLL can be used to multiply
the frequency by two to obtain an fOSC2 of 4 to 8
MHz. The PLL is enabled by option byte. If the PLL
is disabled, then fOSC2 = fOSC/2.
Caution: The PLL is not recommended for appli-
cations where timing accuracy is required. See
“PLL Characteristics” on page 150.
Figure 11. PLL Block Diagram
Figure 12. Clock, Reset and Supply Block Diagram
0
1
PLL OPTION BIT
PLL x 2
fOSC2
/ 2
fOSC
LOW VOLTAGE
DETECTOR
(LVD)
fOSC2
AUXILIARY VOLTAGE
DETECTOR
(AVD)
MULTI-
OSCILLATOR
(MO)
OSC1
RESET
VSS
EVD
VDD
RESET SEQUENCE
MANAGER
(RSM)
OSC2
MAIN CLOCK
AVD Interrupt Request
CONTROLLER
PLL
SYSTEM INTEGRITY MANAGEMENT
WATCHDOG
SICSR
TIMER (WDG)
WITH REALTIME
CLOCK (MCC/RTC)
AVD AVD AVD LVD
RF
IE
WDG
RF
0
1
fOSC
(option)
0
S
F
fCPU
00



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