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PM6641 датащи(PDF) 31 Page - STMicroelectronics

номер детали PM6641
подробное описание детали  Monolithic VR for chipset and DDR2/3 supply for ultra-mobile PC (UMPC) applications
PDF  47 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PM6641 датащи(HTML) 31 Page - STMicroelectronics

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PM6641
Device description
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The synchronous mode of operation provides the following total input current:
Equation 8
whereas by shifting the three regulator turn on pulses of 120 deg the resulting total input
current is given by
Equation 9
that is
times smaller than the one computed before.
The PM6641 SET_PH1 pin, if tied to AVCC, enables the synchronous switching regulators
high side MOSFET turn on, whereas if tied to ground enables the 120 deg phase shifting.
7.10
Peak current limit
The peak current limit performed by the PM6641 switching regulators allows to monitor,
cycle by cycle, the inductor current; this feature prevents IC wire bonding overheating and
failure.
If the current sensed on the monolithic high side MOSFET reaches the programmed current
limit the regulator starts behaving like a current generator, more than a voltage regulator.
Consequently, if the output load still increases the rail output capacitor discharges itself and
the regulator works as current generator until the Output Under Voltage occurs and the
regulator is latched off (see Chapter 7.11.2: Output under voltage on page 33 section for
details).
The pin 4 (CSNS) allows to select the right value for the peak current limit by inserting an
external resistor (RCSNS ) between this pin and ground. CSNS forces a constant voltage on
RCSNS resistor or, when tied to AVCC, enables the internal reference (equal to a 50 k
external resistor). A simple equation shows how to compute the right value for RCSNS in
order to decrease the peak current limit:
Equation 10
()
()
ON
2
SW
T
2
3
L
2
L
1
L
SW
SYNC
,
CIN
T
I
3
T
1
dt
I
I
I
T
1
I
SW
=
+
+
=
()
()
ON
2
2
2
SW
T
2
3
L
2
L
1
L
SW
DELAY
,
CIN
T
I
I
I
T
1
dt
I
I
I
T
1
I
SW
+
+
=
+
+
=
73
.
1
3
CL
REF
CSNS
I
V
R
α
=



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