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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TLC320AD50C/I датащи(PDF) 40 Page - Texas Instruments |
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TLC320AD50C/I датащи(HTML) 40 Page - Texas Instruments |
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40 / 54 page  5–1 5 Parameter Measurement Information SCLK Period/4 2.4 V 0.8 V SCLK FSD 0.8 V td(CH-FDL) FS NOTE A: Timing shown is for the TLC320AD50C/52C operating as the master device. The programmed data value in the FSD register is 0. D0 through D5 of control 3 register are all 0. Figure 5–1. Master FS and FSD Timing td(FL-FDL) 0.8 V 0.8 V FSD FS NOTE A: Timing shown is for the TLC320AD50C/52C operating in the slave mode (FS and SCLK signals are generated externally). The programmed data value in the FSD register is 0. Figure 5–2. Slave FS to FSD Timing td(CH-FDL) 0.8 V SCLK FSD 0.8 V NOTE A: Timing shown is for the TLC320AD50C/52C operating in the slave mode (FS and SCLK signals are generated externally). There is a data value in the FSD register greater than 18 decimal. D0 through D5 of control 3 register are greater than 17. Figure 5–3. Master/Slave SCLK to FSD Timing |
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