STM32F207VCT6 datasheet(38/184 Pages) STMICROELECTRONICS

38 / 184 page

Functional overview

STM32F20xxx

38/184

DocID15818 Rev 15

CAN is used). The 256 bytes of SRAM which are allocated for each CAN are not shared

with any other peripheral.

3.28

Universal serial bus on-the-go full-speed (OTG_FS)

The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated

transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and

with the OTG 1.0 specification. It has software-configurable endpoint setting and supports

suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock

that is generated by a PLL connected to the HSE oscillator. The major features are:

•

Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing

•

Supports the session request protocol (SRP) and host negotiation protocol (HNP)

•

4 bidirectional endpoints

•

8 host channels with periodic OUT support

•

HNP/SNP/IP inside (no need for any external resistor)

•

For OTG/Host modes, a power switch is needed in case bus-powered devices are

connected

•

Internal FS OTG PHY support

3.29

Universal serial bus on-the-go high-speed (OTG_HS)

The STM32F20x devices embed a USB OTG high-speed (up to 480 Mb/s) device/host/OTG

peripheral. The USB OTG HS supports both full-speed and high-speed operations. It

integrates the transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin

interface (ULPI) for high-speed operation (480 MB/s). When using the USB OTG HS in HS

mode, an external PHY device connected to the ULPI is required.

The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG

1.0 specification. It has software-configurable endpoint setting and supports

suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock

that is generated by a PLL connected to the HSE oscillator. The major features are:

•

Combined Rx and Tx FIFO size of 1024× 35 bits with dynamic FIFO sizing

•

Supports the session request protocol (SRP) and host negotiation protocol (HNP)

•

6 bidirectional endpoints

•

12 host channels with periodic OUT support

•

Internal FS OTG PHY support

•

External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is

connected to the microcontroller ULPI port through 12 signals. It can be clocked using

the 60 MHz output.

•

Internal USB DMA

•

HNP/SNP/IP inside (no need for any external resistor)

•

For OTG/Host modes, a power switch is needed in case bus-powered devices are

connected

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