1

2

7

1A

1B

1Y

5

6

3

2A

2B

2Y

SN74LVC2G38

SCES554D – MARCH 2004 – REVISED DECEMBER 2013

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Function Table

(Each Gate)

INPUTS

OUTPUT

Y

A

B

L

L

H

L

H

H

H

L

H

H

H

L

Logic Diagram (Positive Logic)

Absolute Maximum Ratings

(1)

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

VCC

Supply voltage range

–0.5

6.5

V

VI

Input voltage range(2)

–0.5

6.5

V

VO

Voltage range applied to any output in the high-impedance or power-off state (2)

–0.5

6.5

V

VO

Voltage range applied to any output in the high or low state (2) (3)

–0.5

VCC + 0.5

V

IIK

Input clamp current

VI < 0

–50

mA

IOK

Output clamp current

VO < 0

–50

mA

IO

Continuous output current

±50

mA

Continuous current through VCC or GND

±100

mA

DCT package

220

θJA

Package thermal impedance(4)

DCU package

227

°C/W

YZP package

102

Tstg

Storage temperature range

–65

150

°C

(1)

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

(3)

The value of VCC is provided in the recommended operating conditions table.

(4)

The package thermal impedance is calculated in accordance with JESD 51-7.

2

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