1

3

4

A

B

Y

6

C

SN74LVC1G0832

SCES606D – SEPTEMBER 2004 – REVISED DECEMBER 2013

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Function Table(1)

INPUTS

OUTPUT

Y

A

B

C

X

X

H

H

H

H

X

H

X

L

L

L

L

X

L

L

(1)

X = Valid H or L

Logic Diagram (Positive Logic)

Function Selection Table

LOGIC

FIGURE

FUNCTION

2-Input AND Gate

Figure 1

2-Input OR Gate

Figure 2

Y = (A • B) + C

Figure 3

2

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