ISL8117A

FN8752 Rev 1.00

Page 20 of 23

Feb 26, 2024

9. Use copper filled polygons or wide short traces to connect the

junction of upper FET, lower FET and output inductor. Also

keep the PHASE node connection to the IC short. DO NOT

unnecessarily oversize the copper islands for the PHASE

node. Since the phase nodes are subjected to very high dv/dt

voltages, the stray capacitor formed between these islands

and the surrounding circuitry will tend to couple switching

noise.

10. Route all high speed switching nodes away from the control

circuitry.

11. Create a separate small analog ground plane near the IC.

Connect the SGND pin to this plane. All small signal grounding

paths including feedback resistors, current limit setting

resistor, soft-starting capacitor and EN pull-down resistor

should be connected to this SGND plane.

12. Separate the current sensing trace from the PHASE node

connection.

13. Ensure the feedback connection to the output capacitor is

short and direct.

General PowerPAD Design Considerations

The following is an example of how to use vias to remove heat

from the IC.

It is recommended to fill the thermal pad area with vias. A typical

via array fills the thermal pad footprint such that their centers are

3x the radius apart from each other. Keep the vias small but not

so small that their inside diameter prevents solder wicking

through during reflow.

Connect all vias to the ground plane. It is important the vias have

a low thermal resistance for efficient heat transfer. It is

important to have a complete connection of the plated

through-hole to each plane.

Component Selection Guideline

MOSFET Considerations

The logic level MOSFETs are chosen for optimum efficiency given

the potentially wide input voltage range and output power

requirement. Two N-Channel MOSFETs are used in the

synchronous-rectified buck converters. These MOSFETs should be

selected based upon rDS(ON), gate supply requirements and

thermal management considerations.

Power dissipation includes two loss components: conduction

loss and switching loss. These losses are distributed between

the upper and lower MOSFETs according to duty cycle (see

Equations 24 and 25). The conduction losses are the main

component of power dissipation for the lower MOSFET. Only the

upper MOSFET has significant switching losses since the lower

device turns on and off into near zero voltage. The equations

assume linear voltage current transitions and do not model

power loss due to the reverse recovery of the lower MOSFET’s

body diode.

A large gate-charge increases the switching time, tSW, which

increases the upper MOSFETs’ switching losses. Ensure that both

MOSFETs are within their maximum junction temperature at high

ambient temperature by calculating the temperature rise

according to package thermal resistance specifications.

Output Inductor Selection

The PWM converter requires an output inductor. The output

inductor is selected to meet the output voltage ripple

requirements. The inductor value determines the converter’s

ripple current and the ripple voltage is a function of the ripple

current and the output capacitor(s) ESR. The ripple voltage

expression is given in the output capacitor selection section and

the ripple current is approximated by Equation 26:

The ripple current ratio is usually from 30% to 70% of the full

output load.

Output Capacitor Selection

The output capacitors for each output have unique requirements.

In general, the output capacitors should be selected to meet the

dynamic regulation requirements including ripple voltage and

load transients. Selection of output capacitors is also dependent

on the output inductor, so some inductor analysis is required to

select the output capacitors.

One of the parameters limiting the converter’s response to a load

transient is the time required for the inductor current to slew to

its new level. The ISL8117A will provide either 0% or maximum

duty cycle in response to a load transient.

The response time is the time interval required to slew the

inductor current from an initial current value to the load current

level. During this interval, the difference between the inductor

current and the transient current level must be supplied by the

output capacitor(s). Minimizing the response time can minimize

the output capacitance required. Also, if the load transient rise

time is slower than the inductor response time, as in a hard

drive or CD drive, it reduces the requirement on the output

capacitor.

FIGURE 34. PCB VIA PATTERN

PUPPER

IO

2





rDS ON









VOUT





VIN

---------------------------------------------------------------

IO

 

VIN





tSW





fSW





2

----------------------------------------------------------

+

=

(EQ. 24)

PLOWER

IO

2





rDS ON









VIN VOUT

–





VIN

-------------------------------------------------------------------------------

=

(EQ. 25)



IL

VIN VOUT

–





VOUT





fSW





L

 

VIN





----------------------------------------------------------

=

(EQ. 26)