DA9313 datasheet(36/55 Pages) RENESAS

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DA9313

High Efficiency Dual Cell Switched Capacitor Divider

Datasheet

Revision 3.6

16-Jun-2023

CFR0011-120-00

36 of 55

12.2 I2C Control Bus Protocol

Data are transmitted over the I2C bus in groups of 8 bits. To send a bit the SDA line is driven to the

intended state while the SCL is low (for example, a low on SDA indicates a zero bit). Once the SDA

has settled the SCL line is brought high and then low. This pulse on SCL clocks the SDA bit into the

receivers shift register.

DA9313 uses a two byte serial protocol which contains one byte for the address and one byte for

data. Data and address transfer is based on the MSB transmitted first for both read and write

operations. All transmission begins with the START condition from the master as long as the bus is in

IDLE state (the bus is free). The START condition is defined as a high to low transition at the SDA

line while the SCL is high. The STOP condition is defined as a low to high transition at the SDA line

while the SCL is high.

SCL

SDA

Figure 15: Timing of I2C START and STOP Condition

The I2C bus will be monitored by DA9313 for a valid SLAVE address whenever the interface is

enabled. It responds immediately when it receives its own slave address. This acknowledge is done

by pulling the SDA line low during the following clock cycle (white blocks marked with A in Figure 16

to Figure 20).

The protocol for a register write from master to slave consists of a START condition, a slave address

with read/write bit and the 8-bit register address followed by 8 bits of data terminated by a STOP

condition (all bytes responded to by DA9313 with Acknowledge):

SLAVEadr

REGadr

DATA

S = START condition

A = Acknowledge (low)

P = STOP condition

W = Write (low)

Master to Slave

Slave to Master

7-bits

1-bit

8-bits

Figure 16: I2C Byte Write (SDA Line)

When the host reads data from a register it first has to write access DA9313 with the target register

address and then read access DA9313 with a Repeated START or alternatively a second START

condition. After receiving the data the host sends No Acknowledge and terminates the transmission

with a STOP condition:

SLAVEadr W

REGadr

SLAVEadr

S = START condition

A = Acknowledge (low)

Sr = Repeated START condition

* = No Acknowledge

P = STOP condition

W = Write (low)

R = Read (high)

Master to Slave

7-bits

1-bit

8-bits

7-bits

DATA

1-bit

8-bits

SLAVEadr

7-bits

DATA

1-bit

8-bits

Slave to Master

SLAVEadr W

REGadr

7-bits

1-bit

8-bits

Figure 17: I2C Byte Read (SDA Line)

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