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RECEIVER SWITCHING CHARACTERISTICS

SN65MLVD2

SN65MLVD3

SLLS767 – NOVEMBER 2006

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP(1)

MAX

UNIT

tPLH

Propagation delay time, low-to-high-level output

2

6

ns

tPHL

Propagation delay time, high-to-low-level output

2

6

ns

tr

Output signal rise time

1

2.3

tf

Output signal fall time

CL = 15 pF, See Figure 2

1

2.3

ns

Type 1

90

210

tsk(p)

Pulse skew (|tPHL– tPLH|)

ps

Type 2

45

250

tsk(pp)

Part-to-part skew

1

ns

tjit(per)

Period jitter, rms (1 standard deviation)(2)

125 MHz clock input

10

ps

tjit(c-c)

Cycle-to-cycle jitter, rms(3)

125 MHz clock input(4)

8

ps

Type 1

500

ps

tjit(det)

Deterministic jitter(2)

250 Mbps 215-1 PRBS input(5)

Type 2

450

ps

Type 1

8

ps

tjit(ran)

Random jitter(2)

250 Mbps 215-1 PRBS input(5)

Type 2

8

ps

tPZH

Enable time, high-impedance-to-high-level output

CL = 15 pF, See Figure 3

15

ns

tPZL

Enable time, high-impedance-to-low-level output

CL = 15 pF, See Figure 3

15

ns

tPHZ

Disable time, high-level-to-high-impedance output

CL = 15 pF, See Figure 3

10

ns

tPLZ

Disable time, low-level-to-high-impedance output

CL = 15 pF, See Figure 3

10

ns

(1)

All typical values are at 25

°C and with a 3.3-V supply voltage.

(2)

Jitter measured by triggering off of the input source to track out the associated input jitter.

(3)

Stimulus jitter has been subtracted from the numbers.

(4)

Measured over 75K samples

(5)

Measured over BER = 10–6.

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

A

6

I

M-LVDS Non-inverting input

B

7

I

M-LVDS Inverting input

R

3

O

Data output from receivers

RE

2

I

Receiver enable, active low, enables all receivers

GND

4, 5

Circuit ground

VCC

1, 8

Supply voltage

DEVICE FUNCTION TABLES

TYPE-1 RECEIVER (SN65MLVD2)

TYPE-2 RECEIVER (SN65MLVD3)

INPUTS(1)

OUTPUT(1)

INPUTS(1)

OUTPUT(1)

VID = VA– VB

RE

R

VID = VA– VB

RE

R

VID ≥ 35 mV

L

H

VID ≥ 135 mV

L

H

–35 mV

≤ V

ID ≤ 35 mV

L

?

65 mV

≤ V

ID ≤ 135 mV

L

?

VID ≤– 35 mV

L

L

VID ≤ 65 mV

L

L

X

H

Z

X

H

Z

X

Open

Z

X

Open

Z

Open Circuit

L

?

Open Circuit

L

L

(1)

H=high level, L=low level, Z=high impedance, X=Don’t care, ?=indeterminate

5

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