RE6

60

ANE6

—

—

—

—

—

—

—

SMT1WIN1(1)

CCP3(1)

—

—

IOCE6

—

RE7

59

ANE7

—

—

—

—

—

—

—

SMT1SIG1(1)

——

—

IOCE7

—

RF0

18

ANF0

—

C1IN0-

C2IN0-

—

—

—

—

—

—

—

—

—

—

—

RF1

17

ANF1

—

—

—

—

—

—

—

—

—

—

—

—

—

RF2

16

ANF2

—

—

—

—

—

—

—

—

—

—

—

—

—

RF3

15

ANF3

—

C1IN2-

C2IN2-

C3IN2-

——

—

—

—

—

—

—

—

—

—

RF4

14

ANF4

—

C2IN0+

—

—

—

—

—

—

—

—

—

—

—

RF5

13

ANF5

DAC1OUT1

C1IN1-

C2IN1-

——

—

—

—

—

—

—

—

—

—

RF6

12

ANF6

—

C1IN0+

—

—

—

—

—

—

—

—

—

—

—

RF7

11

ANF7

—

C1IN3-

C2IN3-

C3IN3-

—SS1(1)

——

—

—

—

—

—

—

—

RG0

3

ANG0

—

—

—

—

—

—

—

—

—

—

—

—

—

RG1

4

ANG1

—

—

—

—

CK2(3)

——

—

—

—

—

—

—

RG2

5

ANG2

—

C3IN0+

—

—

RX2(1)

DT2(3)

—

—

—

—

—

—

—

—

RG3

6

ANG3

—

C3IN0-

—

—

—

—

—

—

CCP1(1)

——

—

—

RG4

8

ANG4

—

C3IN1-

—

—

—

—

T5G(1)

T7CKI(1)

—

CCP2(1)

—

—

—

—

RG5

7

—

—

—

—

—

—

—

—

—

—

—

—

—

MCLR

VPP

RG6

20

ANG6

—

—

—

—

—

—

—

SMT2WIN1(1)

—

—

—

—

—

RG7

19

ANG7

—

—

—

—

—

—

—

SMT2SIG1(1)

——

—

—

—

RH0

26

—

—

—

—

—

—

—

—

—

—

—

—

—

—

RH1

25

ADCACT(1)

——

—

—

—

—

—

—

—

—

—

—

—

RH2

57

—

—

—

—

—

—

—

—

—

—

—

—

—

—

TABLE 5:

64-PIN ALLOCATION TABLE PIC18(L)F6XK40 (CONTINUED)

Note

1:

This is a PPS remappable signal. The input function may be removed from the default location shown to one of several other PORTx pins. Details about this can be found in the data sheet.

2:

All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several POTRTx pin options. Details about this can be found in the data sheet.

3:

This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.

4:

These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RA5) will operate, but input logic levels will be

standard TTL/ST as selected b the INLVL register, instead of the I2C specific input buffer thresholds.