AM53C96 datasheet(20/63 Pages) AMD

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P R E L I M I N A R Y

AMD

Am53C94/Am53C96

STATREG – Bit 2 – MSG – Message

STATREG – Bit 1 – C/D – Command/Data

STATREG – Bit 0 – I/O – Input/Output

Bit2

Bit1

Bit0

MSG

C/D

I/O

SCSI Phase

Message In

Message Out

Reserved

Status

Command

Data_In

Data_Out

The MSG, C/D and I/O bits together can be referred to

as the SCSI Phase bits. They indicate the phase of the

SCSI bus. These bits may be latched or unlatched de-

pending on the option selected in Control Register 2

(CNTLREG2) by the Latch SCSI Phase (LSP) bit.

In the latched mode the SCSI phase bits are latched at

the end of a command and the latch is opened when the

Interrupt Status Register (INSTREG) is read. In the un-

latched mode, they indicate the phase of the SCSI bus

when this register is read.

SCSI Destination ID Register (04H) Write

RES

00000

SCSI Destination ID Register

SDIDREG

Address: 04H

Type: Write

76543

210

DID2

DID1

DID0

xxx

Reserved

SCSI Destination ID 2:0

Reserved

16506C-21

SDIDREG – Bits 7:3 – RES – Reserved

SDIDREG – Bits 2:0 – DID 2:0 – Destination ID 2:0

The DID 2:0 bits are the encoded SCSI ID of the device

on the SCSI bus which needs to be selected or

reselected.

DID2

DID1

DID0

SCSI ID

1117

1106

1015

1004

0113

0102

0011

0000

At power-up the state of these bits is undefined. The DID 2:0

bits are not affected by reset.

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